74LV74PW,118 NXP Semiconductors, 74LV74PW,118 Datasheet - Page 13

• Manufacturer Part Number: 74LV74PW,118
• Description: IC DUAL D FF POSEDG TRIG 14TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVr
• Type: D-Typer

Specifications of 74LV74PW,118

• Output Type: Differential
• Package / Case: 14-TSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 56MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 12mA, 12mA
• Voltage - Supply: 1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: LV
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 11 ns at 3.3 V
• High Level Output Current: - 12 mA
• Low Level Output Current: 12 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1 V
• Delay Time - Propagation: -
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSSOP
• Frequency (max): 56MHz
• Operating Supply Voltage (min): 1V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 74LV74PW-T; 74LV74PW-T; 935175140118

NXP Semiconductors
Fig 10. Package outline SOT108-1 (SO14)
74LV74_3
Product data sheet
SO14: plastic small outline package; 14 leads; body width 3.9 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
inches
UNIT
mm
VERSION
OUTLINE
SOT108-1
0.069
max.
1.75
A
0.010
0.004
0.25
0.10
A
14
1
1
Z
pin 1 index
y
0.057
0.049
1.45
1.25
A
2
076E06
IEC
0.25
0.01
e
A
3
0.019
0.014
0.49
0.36
b
p
D
0.0100
0.0075
0.25
0.19
MS-012
JEDEC
c
Rev. 03 — 28 September 2007
REFERENCES
8.75
8.55
0.35
0.34
D
(1)
0
Dual D-type flip-flop with set and reset; positive edge-trigger
0.16
0.15
E
4.0
3.8
b
(1)
p
8
7
JEITA
scale
1.27
0.05
2.5
e
w
M
c
0.244
0.228
H
6.2
5.8
E
A
2
0.041
5 mm
1.05
A
L
1
0.039
0.016
1.0
0.4
L
p
H
E
E
0.028
0.024
detail X
0.7
0.6
Q
L
PROJECTION
L
EUROPEAN
0.25
0.01
p
Q
v
(A )
3
0.25
0.01
A
w
0.004
A
0.1
© NXP B.V. 2007. All rights reserved.
X
v
y
M
ISSUE DATE
74LV74
99-12-27
03-02-19
A
0.028
0.012
Z
0.7
0.3
(1)
SOT108-1
8
0
o
o
13 of 19