IDT72T20108L6-7BB IDT, Integrated Device Technology Inc, IDT72T20108L6-7BB Datasheet - Page 8

• Manufacturer Part Number: IDT72T20108L6-7BB
• Description: IC FIFO 327768X20 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20108L6-7BB

• Function: Synchronous
• Memory Size: 640K (32K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20108L6-7BB

NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 24-27 and Figures 5-7.
PIN NUMBER TABLE
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
PIN DESCRIPTION (CONTINUED)
WSDR
(L1)
V
(See below)
V
(See below)
GND
(See below)
Vref
(T3)
D
Q
V
V
GND
DNC
Symbol
DDQ
DDQ
Symbol &
CC
0-19
CC
0-19
Pin No.
(1)
Data Inputs
Data Outputs
+2.5V Supply
O/P Rail Voltage
Ground Pin
Do Not Connect
Write Single Data
Rate
+2.5V Supply
O/P Rail Voltage
Ground Pin
Reference
Voltage
Name
Name
HSTL-LVTTL D0-C3, D1-A4, D2-B4, D3-C4, D4-A5, D5-B5, D6-C5, D7-A6, D8-B6, D9-A7, D10-R7, D11-T7,
HSTL-LVTTL Q0-B10, Q1-A10, Q2-B11, Q3-A11, Q4-B12, Q5-A12, Q6-B13, Q7-A13, Q8-B14, Q9-A14, Q10-T14
OUTPUT
I/O TYPE
INPUT
INPUT
INPUT
INPUT
I/O TYPE
—
LVTTL
INPUT
INPUT
INPUT
INPUT
INPUT
D12-R6, D13-T6, D14-R5, D15-T5, D16-R4, D17-T4, D18-P3, D19-R3
Q11-R14, Q12-T13, Q13-R13, Q14-T12, Q15-R12, Q16-T11, Q17-R11, Q18-T10, Q19-R10
A(1,2), C(6,7), D(4-7), K4, L4, M4, N(4-7), P(5-7), T(1,2)
A(15,16), C(10-13), D(10-13), E13, F(4,13), G(4,14), H(4,14), J14, K14, L14, M13, N(10-13),
P(10-13), T(15,16)
A(8,9), B(8,9), C(8,9), D(8,9), E4, G(7-10,13), H(7-10,13), J(4,7-10,13), K(7-10,13), L13, N(8,9),
P(4,8,9), R(8,9), T(8,9)
A3, B(1-3,15,16), C(1,2,14-16), D(1-3,14-16), E(1,15,16), K2, M(1-3,15,16), N(1-3,14-16), P(1,2,14-16),
R(1,2,15,16)
operate in Double Data Clock mode. This pin must be tied either HIGH or LOW and cannot toggle during
When LOW, this input pin sets the write port to Single Data Clock mode. When HIGH, the write port will
operation.
There are V
This pin should be tied to the desired voltage rail for providing power to the output drivers. Nominally 1.5V
or 1.8V for HSTL, 2.5V for LVTTL.
These are Ground pins are for the core device and must be connected to the GND rail.
This is a Voltage Reference input and must be connected to a voltage level determined in the Recommended
DC Operating Conditions section. This provides the reference voltage when using HSTL class inputs.
If HSTL class inputs are not being used, this pin can be left floating.
CC
supply inputs and must be connected to the 2.5V supply rail.
8
Pin Number
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009