IDT72T20108L6-7BB IDT, Integrated Device Technology Inc, IDT72T20108L6-7BB Datasheet - Page 49

• Manufacturer Part Number: IDT72T20108L6-7BB
• Description: IC FIFO 327768X20 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20108L6-7BB

• Function: Synchronous
• Memory Size: 640K (32K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20108L6-7BB

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
Word width may be increased simply by connecting together the control
GATE
(1)
FIRST WORD FALL THROUGH
DATA IN
SERIAL CLOCK (SCLK)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
For both x10 Input and x10 Output bus Widths: 65,536 x 10, 131,072 x 10, 262,144 x 10 and 524,288 x 10
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
For the x20 Input or x20 Output bus Width: 32,768 x 20, 65,536 x 20, 131,072 x 20 and 262,144 x 20
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
(FWFT)
D
0
- D
m
m
Figure 31. Block Diagram of Width Expansion
#1
72T20108
72T20118
72T20128
72T2098
FIFO
IDT
#1
D
m+1
m
- D
Q
49
n
0
n
- Qm
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can
be created by ORing OR of every FIFO, and separately ORing IR of every
FIFO.
72T20108/72T20118/72T20128 devices. D
40-bit wide input bus and Q
bus. Any word width can be attained by adding additional IDT72T2098/
72T20108/72T20118/72T20128 devices.
Figure 31 demonstrates a width expansion using two IDT72T2098/
72T20108
72T20118
72T20128
72T2098
FIFO
IDT
#2
READ CLOCK (RCLK)
READ CHIP SELECT (RCS)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
Q
m+1
- Q
0
-Q
n
19
from each device form a 40-bit wide output
COMMERCIAL AND INDUSTRIAL
m + n
0
- D
TEMPERATURE RANGES
19
DATA OUT
from each device form a
FEBRUARY 13, 2009
5996 drw34
GATE
(1)