IDT72T20108L6-7BB IDT, Integrated Device Technology Inc, IDT72T20108L6-7BB Datasheet - Page 7

• Manufacturer Part Number: IDT72T20108L6-7BB
• Description: IC FIFO 327768X20 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20108L6-7BB

• Function: Synchronous
• Memory Size: 640K (32K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20108L6-7BB

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
PIN DESCRIPTION (CONTINUED)
RCS
(F14)
REN
(F16)
RSDR
RT
(F15)
SCLK
(H15)
SEN
(J15)
SREN
(J16)
SI
(H16)
SO
(K15)
TCK
(F1)
TDI
(E2)
TDO
(F3)
TMS
(F2)
TRST
(E3)
WCLK
(G1)
WCS
(H2)
WEN
(H1)
(L2)
Symbol &
Pin No.
(2)
(2)
(2)
(2)
(2)
(1)
Read Chip
Select
Read Enable
Read Single
Data Rate
Retransmit
Serial Clock
Serial Input
Enable
Serial Read
Enable
Serial Input
Serial Output
JTAG Clock
JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Input
JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Output
JTAG Mode
Select
JTAG Reset
Write Clock
Write Chip Select HSTL-LVTTL The WCS pin an be regarded as a second WEN input, enabling/disabling write operations.
Write Enable
Name
HSTL-LVTTL RCS provides synchronous enable/disable control of the read port and High-Impedance control of the
HSTL-LVTTL When LOW and in DDR mode, REN along with a rising and falling edge of RCLK will send data in FIFO
HSTL-LVTTL SEN used in conjunction with SI and SCLK enables serial loading of the programmable flag offsets.
HSTL-LVTTL SREN used in conjunction with SO and SCLK enables serial reading of the programmable flag offsets.
HSTL-LVTTL This input pin is used to load serial data into the programmable flag offsets. Used in conjunction with SEN
HSTL-LVTTL This output pin is used to read data from the programmable flag offsets. Used in conjunction with SREN
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not
HSTL-LVTTL Input clock when used in conjunction with WEN for writing data into the FIFO memory.
HSTL-LVTTL When LOW and in DDR mode, WEN along with a rising and falling edge of WCLK will write data into the
HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the read pointer to the first location in memory. EF flag
I/O TYPE
OUTPUT
OUTPUT
INPUT
LVTTL
INPUT
LVTTL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Qn data outputs, synchronous to RCLK. When using RCS the OE pin must be tied LOW. During Master
or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance regardless
of RCS.
memory to the output register and read the current data in output register. In SDR mode data will only
be read on the rising edge of RCLK only.
When LOW, this input pin sets the read port to Single Data Clock mode. When HIGH, the read port will
operate in Double Data Clock mode. This pin must be tied either HIGH or LOW and cannot toggle during
operation.
is set to LOW (OR to HIGH in FWFT mode). The write pointer, offset registers, and flag settings are not
affected. If a mark has been set via the MARK input pin, then the read pointer will initialize to the mark location
when RT is asserted.
A rising edge of SCLK will clock the serial data present on the SI input into the offset registers provided
that SEN is enabled. A rising edge of SCLK will also read data out of the offset registers provided that SREN
is enabled.
and SCLK.
and SCLK.
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register,
ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in
SHIFT-DR and SHIFT-IR controller states.
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH
for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be in high-
impedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied
with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be
tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected.
FIFO memory. In SDR mode data will only be read on the rising edge of RCLK only.
7
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009