IDT72T20108L6-7BB IDT, Integrated Device Technology Inc, IDT72T20108L6-7BB Datasheet - Page 15

• Manufacturer Part Number: IDT72T20108L6-7BB
• Description: IC FIFO 327768X20 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20108L6-7BB

• Function: Synchronous
• Memory Size: 640K (32K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20108L6-7BB

NOTES:
1. The programming sequence applies to both IDT Standard and FWFT modes.
2. When the input or output ports are in DDR mode, the depth is reduced by half but the overall density remains the same. For example, the IDT72T2098 in SDR mode is
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
WSDR
32,768 x 20/65,536 x 10 = 655,360, in DDR mode the configuration becomes 16,384 x 40/32,768 x 20 = 655,360. In both cases, the total density are the same.
X
X
1
0
1
1
X
RSDR
X
X
1
1
1
0
X
WEN
1
1
0
0
1
1
1
REN
1
1
1
1
0
0
1
SEN
1
X
0
X
X
X
X
Figure 3. Programmable Flag Offset Programming Sequence
SREN
0
X
1
X
X
X
X
WCLK
X
X
X
X
X
RCLK
X
X
X
X
X
SCLK
X
X
X
X
X
15
Serial Write to registers:
In SDR Mode:
32 bits for the IDT72T2098
34 bits for the IDT72T20108
36 bits for the IDT72T20118
38 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Write to registers:
In DDR Mode:
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Read From registers:
In SDR Mode:
32 bits for the IDT72T2098
34 bits for the IDT72T20108
36 bits for the IDT72T20118
38 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Read from registers:
In DDR Mode:
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Write Memory (DDR)
Write Memory (SDR)
Read Memory (DDR)
Read Memory (SDR)
No Operation
x10 to x10 Mode
x10 to x10 Mode
IDT72T2098
IDT72T20108
IDT72T20118
IDT72T20128
COMMERCIAL AND INDUSTRIAL
Serial Write to registers:
In SDR Mode:
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Write to registers:
In DDR Mode:
28 bits for the IDT72T2098
30 bits for the IDT72T20108
32 bits for the IDT72T20118
34 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Read from registers:
In SDR Mode:
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Read from registers:
In DDR Mode:
28 bits for the IDT72T2098
30 bits for the IDT72T20108
32 bits for the IDT72T20118
34 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
TEMPERATURE RANGES
All Other Modes
All Other Modes
FEBRUARY 13, 2009
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