IDT72V295L15PF IDT, Integrated Device Technology Inc, IDT72V295L15PF Datasheet - Page 22

• Manufacturer Part Number: IDT72V295L15PF
• Description: IC FIFO SUPERSYNCII 15NS 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V295L15PF

• Function: Synchronous
• Memory Size: 2.3K (64 x 36)
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 2.25Mb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 128Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 60mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V295L15PF

NOTE:
1. OE = LOW
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
D
Q
WCLK
RCLK
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
WCLK
WEN
0
REN
0
PAF
In IDT Standard mode: D = 131,072 for the IDT72V295 and 262,144 for the IDT72V2105.
In FWFT mode: D = 131,073 for the IDT72V295 and 262,145 for the IDT72V2105.
RCLK and the rising edge of WCLK is less than t
RCLK
WEN
SKEW2
- Q
REN
- D
LD
LD
15
15
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKH
t
DATA IN OUTPUT REGISTER
CLKH
t
CLKH
TM
PAE OFFSET
131,072 x 18, 262,144 x 18
t
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
ENS
t
(LSB)
CLK
t
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
CLK
t
t
ENS
t
LDS
DS
t
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
ENS
t
t
CLKL
LDS
t
CLKL
D - (m+1) words in FIFO
t
CLKL
t
ENH
SKEW2
t
t
PAE OFFSET
t
ENH
, then the PAF deassertion time may be delayed one extra WCLK cycle.
DH
LDH
t
t
LDH
t
ENH
A
(MSB)
1
(2)
PAE OFFSET
(LSB)
PAF OFFSET
2
(LSB)
t
PAF
22
t
ENS
t
SKEW2
PAE OFFSET
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
(MSB)
(3)
PAF OFFSET
(MSB)
t
ENH
D - m words in FIFO
1
t
t
LDH
ENH
PAF OFFSET
t
(LSB)
DH
(2)
t
t
ENH
LDH
PAF
t
). If the time between the rising edge of
A
2
t
PAF
D-(m+1) words
in FIFO
PAF OFFSET
4668 drw 19
4668 drw 17
(MSB)
4668 drw 18
(2)