IDT72V835L15PF IDT, Integrated Device Technology Inc, IDT72V835L15PF Datasheet - Page 8

• Manufacturer Part Number: IDT72V835L15PF
• Description: IC FIFO SYNC 2048X18 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V835L15PF

• Function: Asynchronous, Synchronous
• Memory Size: 36.8K (2K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V835L15PF

TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET
NOTES:
1. In a daisy-chain depth expansion, FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.
2. In a daisy-chain depth expansion, FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding RXO
TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE
TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD MODE
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
and WXO outputs of the preceding device.
0
1
FL
Output Ready (OR)
0
0
0
1
1
1
(1)
(2)
Empty Flag (EF)
Buffered Output
Double
Double
Single
Single
Triple
Triple
RXI
0
0
1
1
0
0
1
1
WXI
0
1
0
1
0
1
0
1
Single Register-Buffered
Empty Flag
Triple Register-Buffered
Output Ready Flag
Double Register-Buffered
Empty Flag
Single Register-Buffered
Empty Flag
Single Register-Buffered
Empty Flag
Triple Register-Buffered
Output Ready Flag
Double Register-Buffered
Empty Flag
Single Register-Buffered
Empty Flag
Buffered Output
Input Ready (IR)
Full Flag (FF)
Double
Double
Double
Double
Single
Single
EF/OR
Timing Mode
Partial Flags
Partial Flags
Single Register-Buffered
Full Flag
Double Register-Buffered
Input Ready Flag
Double Register-Buffered
Full Flag
Single Register-Buffered
Full Flag
Single Register-Buffered
Full Flag
Double Register-Buffered
Input Ready Flag
Double Register-Buffered
Full Flag
Single Register-Buffered
Full Flag
Asynch
Asynch
Synch
Asynch
Sync
Sync
8
FF/IR
FL
FL
0
1
0
0
1
Programming at Reset
1
Programming at Reset
RXI
RXI
0
0
0
0
1
1
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Asynchronous
PAE, PAF
COMMERCIAL AND INDUSTRIAL
WXI
WXI
1
0
1
0
0
0
TEMPERATURE RANGES
FIFO TIMING MODE
FEBRUARY 11, 2009
Figure 20, 21
Flag Timing
Figure 24, 26
Figure 24, 26
Flag Timing
Figure 9, 10
Figure 9, 10
Standard
Standard
Standard
Standard
Standard
Standard
Diagrams
Diagrams
Figure 27
FWFT
FWFT