IDT72V835L15PF IDT, Integrated Device Technology Inc, IDT72V835L15PF Datasheet - Page 25

• Manufacturer Part Number: IDT72V835L15PF
• Description: IC FIFO SYNC 2048X18 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V835L15PF

• Function: Asynchronous, Synchronous
• Memory Size: 36.8K (2K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V835L15PF

of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO’s outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the
t
and transfer clock, for the OR flag.
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
configuration will “bubble up” from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
SKEW1
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
PAF
HF
WRITE ENABLE
INPUT READY
DATA IN
WRITE CLOCK
For an empty expansion configuration, the amount of time it takes for OR
(N – 1)*(4*transfer clock) + 3*T
The “ripple down” delay is only noticeable for the first word written to an
The first free location created by reading from a full depth expansion
specification is not met between WCLK and transfer clock, or RCLK
n
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 Synchronous FIFO Memory
IR
Dn
WCLK
WEN
(0,1)
FL
RCLK
72V805
72V815
72V825
72V835
72V845
GND
RXI
with Programmable Flags Used in Depth Expansion Configuration
TRANSFER CLOCK
WXI
V
CC
RCLK
REN
OR
OE
Qn
RCLK
is the RCLK
GND
n
25
created in one FIFO of the chain, that FIFO’s IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the
t
and transfer clock, for the IR flag.
whichever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
SKEW1
For a full expansion configuration, the amount of time it takes for IR of the
The Transfer Clock line should be tied to either WCLK or RCLK,
(N – 1)*(3*transfer clock) + 2 T
specification is not met between RCLK and transfer clock, or WCLK
WCLK
IR
Dn
WEN
(0,1)
FL
72V805
72V815
72V825
72V835
72V845
GND
RXI
COMMERCIAL AND INDUSTRIAL
WCLK
WXI
V
TEMPERATURE RANGES
RCLK
CC
REN
OR
OE
Qn
FEBRUARY 11, 2009
OUTPUT ENABLE
n
OUTPUT READY
WCLK
READ ENABLE
READ CLOCK
DATA OUT
is the WCLK
4295 drw 31
PAE
HF