IDT72V835L15PF IDT, Integrated Device Technology Inc, IDT72V835L15PF Datasheet - Page 14

no-image

IDT72V835L15PF

Manufacturer Part Number
IDT72V835L15PF
Description
IC FIFO SYNC 2048X18 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V835L15PF

Function
Asynchronous, Synchronous
Memory Size
36.8K (2K x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V835L15PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V835L15PF
Manufacturer:
IDT
Quantity:
12
Part Number:
IDT72V835L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V835L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V835L15PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V835L15PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
Q
D
NOTES:
1. When t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Q
of RCLK and the rising edge of WCLK is less than t
D
0
0
SKEW1
WCLK
RCLK
Latency Timing apply only at the Empty Boundary (EF = LOW).
- Q
0
0
- D
WEN
WCLK
RCLK
REN
WEN
- Q
- D
REN
OE
EF
OE
17
17
FF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge
17
17
SKEW1
t
t
ENS
LOW
DS
LOW
minimum specification, t
DATA IN OUTPUT REGISTER
t
ENS
DATA WRITE 1
t
SKEW1
NO WRITE
t
t
ENH
SKEW1
(1)
DATA IN OUTPUT REGISTER
Figure 10. Single Register-Buffered Empty Flag Timing (IDT Standard Mode)
FRL
Figure 9. Single Register-Buffered Full Flag Timing (IDT Standard Mode)
(maximum) = t
t
ENH
t
t
A
FRL
SKEW1
(1)
t
, then FF may not change state until the next WCLK edge.
WFF
CLK
t
REF
+ t
SKEW1
t
DS
. When t
DATA WRITE
SKEW1
14
t
WFF
< minimum specification, t
t
A
t
REF
DATA READ
t
ENS
t
t
ENS
DS
t
SKEW1
FRL
DATA WRITE 2
NO WRITE
(maximum) = either 2 * t
(1)
t
ENH
t
SKEW1
COMMERCIAL AND INDUSTRIAL
DATA READ
t
ENH
t
A
t
TEMPERATURE RANGES
FRL
CLK
t
WFF
(1)
+ t
SKEW1
FEBRUARY 11, 2009
NEXT DATA READ
t
REF
, or t
t
CLK
DS
4295 drw 09
+ t
4295 drw 10
SKEW1
DATA
WRITE
. The

Related parts for IDT72V835L15PF