XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 79

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Functional Description
determines how the FPGA generates addresses, as shown
Table
starting at 0 and increments the address on every falling
CCLK edge. Conversely, when M0 = 1, the FPGA gener-
ates addresses starting at 0xFF_FFFF (all ones) and decre-
ments the address on every falling CCLK edge.
Table 50: BPI Addressing Control
This addressing flexibility allows the FPGA to share the par-
allel Flash PROM with an external or embedded processor.
72
A
M2
0
During configuration, the value of the M0 mode pin
50. When M0 = 0, the FPGA generates addresses
M1
Figure 55: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
1
Recommend
open-drain
PROG_B
M0
0
1
driver
TMS
TDO
TCK
TDI
+2.5V
JTAG
Start Address
0xFF_FFFF
0
Not available
in VQ100
package
BPI Mode
‘0’
‘1’
‘0’
‘0’
P
A
Incrementing
Decrementing
Addressing
HSWAP
M2
M1
M0
CSI_B
RDWR_B
TDI
TMS
TCK
PROG_B
Spartan-3E
FPGA
VCCINT
+1.2V
GND
www.xilinx.com
VCCAUX
VCCO_0
VCCO_1
VCCO_2
A[23:17]
CSO_B
A[16:0]
INIT_B
DONE
BUSY
D[7:0]
CCLK
LDC0
LDC1
LDC2
HDC
TDO
Depending on the specific processor architecture, the pro-
cessor boots either from the top or bottom of memory. The
FPGA is flexible and boots from the opposite end of mem-
ory from the processor. Only the processor or the FPGA can
boot at any given time. The FPGA can configure first, hold-
ing the processor in reset or the processor can boot first,
asserting the FPGA’s PROG_B pin.
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are avail-
able as full-featured user-I/O pins.
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
P
Similarly, the FPGA’s HSWAP pin must be Low to
VCCO_0
+2.5V
V
V
V
I
Advance Product Specification
CE#
OE#
WE#
BYTE#
DQ[15:7]
DQ[7:0]
A[n:0]
DS312-2 (v1.1) March 21, 2005
DS312-2_49_022305
VCCO
GND
V
x8/x16
PROM
Flash
x8 or
+2.5V
D
R