XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 171

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Pinout Descriptions
User I/Os by Bank
Table
user-I/O pins are distributed between the four I/O banks on
the FG320 package.
Table 25: User I/Os Per Bank for XC3S500E in the FG320 Package
Table 26: User I/Os Per Bank for XC3S1200E in the FG320 Package
Table 27: User I/Os Per Bank for XC3S1600E in the FG320 Package
Footprint Migration Differences
Table 28
ences between the XC3S500E, the XC3S1200E, and the
XC3S1600E FPGAs that may affect easy migration
between devices available in the FG320 package. There are
26 such balls. All other pins not listed in
tionally migrate between Spartan-3E devices available in
the FG320 package.
50
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Package
Package
Package
Edge
Edge
Edge
25,
summarizes any footprint and functionality differ-
Table
26, and
I/O Bank
I/O Bank
I/O Bank
0
1
2
3
0
1
2
3
0
1
2
3
Table 27
indicate how the available
Maximum
Maximum
Maximum
232
250
250
I/O
I/O
I/O
58
58
58
58
61
63
63
63
61
63
63
63
Table 28
uncondi-
102
120
119
I/O
I/O
I/O
29
22
17
34
34
25
23
38
33
25
23
38
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The XC3S500E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S1200E
and the XC3S1600E. The arrows indicate the direction for
easy migration. A double-ended arrow (
the two pins have identical functionality. A left-facing arrow
( ) indicates that the pin on the device on the right uncon-
ditionally migrates to the pin on the device on the left. It may
be possible to migrate the opposite direction depending on
the I/O configuration. For example, an I/O pin (Type = I/O)
INPUT
INPUT
INPUT
14
10
13
11
48
12
12
11
12
47
13
12
11
12
48
All Possible I/O Pins by Type
All Possible I/O Pins by Type
All Possible I/O Pins by Type
DUAL
DUAL
DUAL
21
24
46
21
24
46
21
24
46
1
0
1
0
1
0
Advance Product Specification
DS312-4 (v1.1) March 21, 2005
VREF
VREF
VREF
20
21
21
6
5
4
5
6
5
5
5
6
5
5
5
) indicates that
GCLK
GCLK
GCLK
16
16
16
8
0
0
8
8
0
0
8
8
0
0
8
R