XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 10

no-image

XC3S250E

Manufacturer Part Number
XC3S250E
Description
Spartan-3E FPGA Family
Manufacturer
Xilinx, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC3S250E
Manufacturer:
XILINX
0
Part Number:
XC3S250E
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC3S250E FTG256
Manufacturer:
XILINX
0
Part Number:
XC3S250E-4CP132C
Manufacturer:
XILINX
Quantity:
435
Part Number:
XC3S250E-4CP132C
Manufacturer:
XILINX
0
Part Number:
XC3S250E-4CP132I
Manufacturer:
XILINX
0
Part Number:
XC3S250E-4CP132I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC3S250E-4CPG132C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC3S250E-4CPG132C
Quantity:
306
Part Number:
XC3S250E-4CPG132CS1
Manufacturer:
SANYO
Quantity:
1 000
Company:
Part Number:
XC3S250E-4CPG132I
Quantity:
118
Input Delay Functions
Each IOB has a programmable delay block that can delay
the input signal from 0 to nominally 4000 ps. In
signal is first delayed by either 0 or 2000 ps (nominal) and is
then applied to an 8 tap delay line. This delay line has a
nominal value of 250 ps per tap. All 8 taps are available via
a multiplexer for use as an asynchronous input directly into
the FPGA fabric. In this way, the delay is programmable
from 0 to 4000 ps in 250 ps steps. Four of the 8 taps are
also available via a multiplexer to the D inputs of the syn-
chronous storage elements. The delay inserted in the path
to the storage element can be varied from 0 to 4000 ps in
500 ps steps. The first, coarse delay element is common to
both asynchronous and synchronous paths, and must be
either used or not used for both paths.
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
PAD
Figure 2: Input Delay Elements
Figure
2, the
www.xilinx.com
The delay values are set up in the silicon once at configura-
tion time—they are non-modifiable in device operation.
The primary use for the input delay element is as an ade-
quate delay to ensure that there is no hold time requirement
when using the input flip-flop(s) with a global clock. The
necessary value for this function is chosen by the Xilinx soft-
ware tools and depends on device size. If the design is
using a DCM in the clock path, then the delay element can
be safely set to zero in the user's design, and there is still no
hold time requirement.
Both asynchronous and synchronous values can be modi-
fied by the user, which is useful where extra delay is
required on clock or data inputs, for example, in interfaces to
various types of RAM.
See
for the delay elements.
Module 3
Asynchronous input (I)
Synchronous input (IQ1)
Synchronous input (IQ2)
of the Spartan-3E data sheet for exact values
D Q
D Q
DS312-2_18_022205
Functional Description
3

Related parts for XC3S250E