XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 118

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Table 18: Timing for the Slave Parallel Configuration Mode
DS312-3 (v1.0) March 1, 2005
Advance Product Specification
INIT_B
CS_B
RDWR_B
CCLK
D0 - D7
BUSY
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
T
PROG_B
(Input)
(Open-Drain)
(Input)
(Input)
(Input)
(Inputs)
(Output)
SMCKBY
SMDCC
SMCSCC
SMCCW
Symbol
It is possible to abort configuration by pulling CS_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CS_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
(2)
R
The time from the rising transition on the CCLK pin to a signal transition at the
BUSY pin
The time from the setup of data at the D0-D7 pins to the rising transition at the
CCLK pin
The time from the setup of a logic level at the CS_B pin to the rising transition
at the CCLK pin
The time from the setup of a logic level at the RDWR_B pin to the rising
transition at the CCLK pin
High-Z
Figure 5: Waveforms for Slave Parallel Configuration
T
SMCCW
T
SMDCC
Description
Byte 0
T
SMCSCC
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T
SMCCD
Byte 1
T
SMCKBY
T
CCH
DC and Switching Characteristics
BUSY
1/F
Byte n
CCPAR
All Speed Grades
T
SMCKBY
10.0
10.0
10.0
Min
-
T
T
CCL
SMCCCS
Byte n+1
Max
12.0
-
-
-
DS312-3_02_020805
T
SMWCC
Units
ns
ns
ns
ns
High-Z
15