XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 137

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
16
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L04N_2/D6/GCLK13
IO_L04P_2/D7/GCLK12
IO_L05N_2/D3/GCLK15
IO_L05P_2/D4/GCLK14
IO_L07N_2/D1/GCLK3
IO_L07P_2/D2/GCLK2
IO_L08N_2/DIN/D0
IO_L08P_2/M0
IO_L09N_2/VS1/A18
IO_L09P_2/VS2/A19
IO_L10N_2/CCLK
IO_L10P_2/VS0/A17
IP
IP
IP
IP_L03N_2/VREF_2
IP_L03P_2
IP_L06N_2/M2/GCLK1
IP_L06P_2/RDWR_B/GCLK0
VCCO_2
VCCO_2
VCCO_2
IP/VREF_3
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
XC3S100E Pin Name
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L04N_2/D6/GCLK13
IO_L04P_2/D7/GCLK12
IO_L05N_2/D3/GCLK15
IO_L05P_2/D4/GCLK14
IO_L07N_2/D1/GCLK3
IO_L07P_2/D2/GCLK2
IO_L08N_2/DIN/D0
IO_L08P_2/M0
IO_L09N_2/VS1/A18
IO_L09P_2/VS2/A19
IO_L10N_2/CCLK
IO_L10P_2/VS0/A17
IP
IP
IP
IP_L03N_2/VREF_2
IP_L03P_2
IP_L06N_2/M2/GCLK1
IP_L06P_2/RDWR_B/GCLK0
VCCO_2
VCCO_2
VCCO_2
IO/VREF_3
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
www.xilinx.com
XC3S250E Pin Name
TQ144 Pin
P40
P39
P44
P43
P51
P50
P54
P53
P59
P58
P63
P62
P68
P67
P71
P70
P38
P41
P69
P48
P47
P57
P56
P42
P49
P64
P31
P15
P14
P3
P2
P5
P4
P8
P7
Advance Product Specification
DS312-4 (v1.1) March 21, 2005
100E: VREF(INPUT)
250E: VREF(I/O)
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
LHCLK
LHCLK
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
R