XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 113

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

DC and Switching Characteristics
Switching Characteristics
All Spartan-3E FPGAs ship in two speed grades: –4 and the
higher performance –5. Switching characteristics in this
document may be designated as Advance, Preliminary, or
Production, as shown in
as follows:
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this des-
ignation are considered relatively stable and conservative,
some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device family mem-
ber has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
Production-quality systems must use FPGA designs com-
piled using a speed file designated as Production status.
FPGAs designs using a less mature speed file designation
should only be used during system prototyping or pre-pro-
duction qualification. FPGA designs with speed files desig-
nated as Preview, Advance, or Preliminary should not be
used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, Xilinx recommends
rerunning the Xilinx ISE software on the FPGA design. This
ensures that the FPGA design incorporates the latest timing
information and software updates.
All specified limits are representative of worst-case supply
voltage and junction temperature conditions. Unless other-
wise noted, the following applies: Parameter values apply to
all Spartan-3E devices. All parameters representing volt-
ages are measured with respect to GND.
Timing parameters and their representative values are
selected for inclusion below either because they are impor-
tant as general design requirements or they indicate funda-
mental device performance characteristics. The Spartan-3E
speed files (v1.10), part of the Xilinx Development Software,
are the original source for many but not all of the values.
The speed grade designations for these files are shown in
Table
10
11. For more complete, more precise, and worst-case
Table
11. Each category is defined
www.xilinx.com
data, use the values reported by the Xilinx static timing ana-
lyzer (TRACE in the Xilinx development software) and
back-annotated to the simulation netlist.
Table 11: Spartan-3E v1.10 Speed Grade Designations
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital Fre-
quency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applica-
tions. All such applications inevitably use the CLKIN and the
CLKFB inputs connected to either the CLK0 or the CLK2X
feedback, respectively. Thus, specifications in the DLL
tables
only employs the DLL component. When the DFS and/or
the PS components are used together with the DLL, then
the specifications listed in the DFS and PS tables super-
sede any corresponding ones in the DLL tables. (See
Table 14
yet available.) DLL specifications that do not change with
the addition of DFS or PS functions are presented in
Table 12
All DCM clock output signals exhibit an approximate duty
cycle of 50%.
Period jitter and cycle-cycle jitter are two (of many) different
ways of characterizing clock jitter. Both specifications
describe statistical variation from a mean value.
Period jitter is the worst-case deviation from the average
clock period of all clock cycles in the collection of clock peri-
ods sampled (usually from 100,000 to more than a million
samples for specification purposes). In a histogram of
period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock peri-
ods sampled. In a histogram of cycle-cycle jitter, the mean
value is zero.
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
System
Usage
Device
(Table 12
and
and
Table 15
Table
Preview
and
–4
–4
–4
–4
–4
13.
Table
Prototyping Only
for the DFS; tables for the PS are not
Advance
13) apply to any application that
Advance Product Specification
DS312-3 (v1.0) March 1, 2005
Preliminary
Production
Production
R