IMP16C554 IMP Inc, IMP16C554 Datasheet - Page 7

• Manufacturer Part Number: IMP16C554
• Description: Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
• Manufacturer: IMP Inc

7
transmitter are controlled separately either
one or both can in the polled mode operation
by utilizing the Line status Register.
A) LSR BIT-0 will be set as long as there is
B) LSR BIT4-1 will specify which error(s) has
C) LSR
D) LSR BIT-6 will indicate when both transmit
E) LSR BIT-6 will indicate when there are
The MS16C554 requires to have two step FIFO
enable operation in order to enable receive trigger
levels.
PROGRAMMABLE BAUD RATE
GENERATOR
The IMP16C554 contains a programmable Baud
Rate Generator that is capable of taking any
clock input from DC-24 MHz and dividing it by
any divisor from 1 to 2
frequency of the Baud out* is equal to 16X of
transmission baud rate (Baudout*=16 x Baud
Rate).
achieved by selecting proper divisor values for
MSB and LSB of baud rate generator.
INTERRUPT ENABLE REGISTER (IER)
The interrupt Enable Register (IER) masks the
incoming interrupts from receiver ready,
transmitter empty, line status and modem
status registers to the INT output pin.
IER BIR-0
0=disable the receiver ready interrupt.
1=enable the receiver ready interrupt.
IER BIR-1
0=disable the transmitter empty interrupt.
1=enable the transmitter empty interrupt.
IER BIR-2
0=disable the receiver line status interrupt.
1=enable the receiver line status interrupt.
IER BIR-3
0=disable the modem status register interrupt.
1=enable the modem status register interrupt.
IER BIR7-4
All these bits are set to logic zero.
INTERRUPT STATUS REGISTER (ISR)
one byte in the receive FIFO.
occurred.
transmit FIFO is empty.
FIFO and transmit shift register are empty.
any errors in the receive FIFO.
Customize
BIT-5
will
Baud
indicate
Rates
16
-1.The output
when
408-432-9100/www.impweb.com
can
the
be
The IMP16C554 provides four level prioritized
interrupt conditions to minimize software
overhead during data character transfers. The
interrupt Status Register (ISR) provides the
source of the interrupt in prioritized matter.
During the read cycle the IMP16C554 provides
the highest interrupt level to be serviced by
CPU. No other interrupts are acknowledged
until the particular interrupt is serviced. The
following sre the prioritized interrupt levels:
Priority level
P
1
2
2*
3
4
*RECEIVE TIME-OUT:
This mode is enabled when the
UART is operating in FIFO mode. Receive
time out will not occur if the receive FIFO is
empty. The time out counter will be reset at
the center of each stop bit received or each
time out value is T (Time out length in bits)=4
X P (Programmed word length)+12. To
convert time out value to a character value,
user has to divide this number to its complete
word length + parity (if used)+number of stop
bits and start bit.
Example-A: if user programs the word
length=7,and no parity and one stop bit. Time
out
length)+12=40 bits Character time =40 / 9
bit=1)+(start bi=1)=4.4 characters.
Example-B: if user programs the word
length=7,with parity and one stop bit, the time
out
length)+12=40 bits Character time =40 / 10
(programmed word length=7) + (parity=1) +
(programmed
D3
0
0
1
0
0
will
will
D2
1
1
1
0
0
be:
IMP16C554
be:T=4x7(programmed
IMP16C554
C1
1
0
0
1
0
T=4x7
word
D0
0
0
0
0
0
(programmed
Source
interrupt
LSR (Receiver Line
Status Register)
RXRDY
Data Ready)
RXRDY
Data time out)
TXRDY
Holding
Empty)
MSR (Modem Status
Register)
length=7)+(stop
(Transmitter
(Received
(Received
of
Register
word
word
the
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