IMP16C554 IMP Inc, IMP16C554 Datasheet - Page 10

• Manufacturer Part Number: IMP16C554
• Description: Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
• Manufacturer: IMP Inc

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LSR BIT-2:
0=no parity error (normal).
1= parity error, received data does not have
correct parity information. In the FIFO mode
this error is associated with the character at
the top of the FIFO.
LSR BIT-3:
0=no framing error (normal).
1=framing error received, received data did
not have a valid stop bit. In the FIFO mode
this error is associated with the character at
the top of the FIFO.
LSR BIT-4:
0=no break condition (normal).
1=receiver received a break signal (RX was
low for one character time frame). In FIFO
mode, only one zero character is loaded into
the FIFO.
LSR BIT-5:
0=transmit holding register is full. IMP16C554
will not accept any data for transmission.
1= transmit holding register (or FIFO) is empty.
CPU can load the next character.
LSR BIT-6:
0=transmit holding register and shift register
are full.
1=transmit holding register and shift register
are empty. In FIFO mode this bit is set to one
whenever the transmitter FIFO and transmit
shift register are empty.
LSR BIT-7:
0= Normal.
1= At least one parity error, framing error or
break indication in the FIFO. This bit is
cleared when LSR is read.
MODEM STATUS REGISTER (MSR)
This register provides the current state of the
control lines from the modem or peripheral to
the CPU. Four bits of this register are used to
indicate the changed information. These bits
are set to “1” whenever a control input from
the MODEM changes state. They are set to
“0” whenever the CPU reads this register.
MSR BIT-0:
Indicates that the CTS* input to the IMP16C554
has changed state since the last time it was
read.
MSR BIT-1:
408-432-9100/www.impweb.com
Indicates that the DSR* input to the IMP16C554
has changed state since the last time it was
read.
MSR BIT-2:
Indicates that the RI* input to the IMP16C554
has changed from a low to a high state.
MSR BIT-3:
Indicates that the CD* input to the ST16C554
has changed state since the last time it was
read.
MSR BIT-4
This bit is equivalent to RTS in the MCR
during local loop-back mode. It is the
compliment of the CTS* input.
MSR BIT-5:
This bit is equivalent to DTR in the MCR
during local loop-back mode. It is the
compliment of the DSR* input.
MSR BIT-6:
This bit is equivalent to MCR bit-2 during local
loop-back mode. It is the compliment of the
RI* input.
MSR BIT-7:
This bit is equivalent to INT enable in the
MCR during local loop-back mode. It is the
compliment of the CD* input.
Note: whenever MSR BIT3-0: is set to logic
“1”, a MODEM Status Interrupt is generated.
SCRATCHPAD REGISTER (SR)
IMP16C554 provides a temporary data register
to store 8 bits of information for variable use.
BAUD RATE GENERATOR PROGRAMMING
TABLE (1.8432 MHz CLOCK):
BAUD
RATE
1200
2400
4800
7200
9600
150
300
600
110
50
IMP16C554
IMP16C554
16 x CLOCK
DIVISOR
2304
1047
768
384
192
96
48
24
16
12
% ERROR
0.026
© 2002 IMP, Inc.