IMP16C554 IMP Inc, IMP16C554 Datasheet - Page 5

• Manufacturer Part Number: IMP16C554
• Description: Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
• Manufacturer: IMP Inc

5
IMP16C554 ACCESSIBLE REGISTERS
DLL and DLM are accessible only when LCR bit-7 is set to “1”.
A2A1A0
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
Registe
r
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
BIT-7
bit-7
bit-7
RCV
R
trigge
r
(MSB
)
0/FIF
Os
enabl
ed
Divis
or
latch
enabl
e
0
o/FIF
O
error
CD
bit-7
bit-7
bit-15
0
BIT-6
bit-6
bit-6
RCV
R
trigge
r
(LSB)
0/FIF
Os
enabl
ed
Set
break
0
trans
empt
y
RI
bit-6
bit-6
bit-14
0
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BIT-5
bit-5
bit-5
Set
parity
0
trans
holdi
ng
empt
y
DSR
bit-5
bit-13
bit-5
0
0
0
BIT-4
bit-4
bit-4
0
Even
parity
Loop
back
break
interr
upt
CTS
bit-4
bit-12
bit-4
0
0
BIT-3
bit-3
Modem
status
interrup
t
DMA
Mode
select
int
priority
bit-2
Parity
enable
INT
enable
framing
error
delta
CD*
bit-3
bit-11
bit-3
bit-3
IMP16C554
IMP16C554
BIT-2
bit-2
bit-2
Receiv
e line
status
interru
pt
XMITF
IFO
reset
Int
priority
bit-1
Stop
bits
Not
used
parity
error
delta
RI*
bit-2
bit-2
bit-10
bit-1
bit-1
Transmi
t
holding
register
RCVRF
IFO
reset
Int
priority
bit-0
Word
length
bit-1
RTS*
overrun
error
delta
DSR*
bit-1
bit-1
bit-9
BIT-1
bit-0
Receive
holding
register
FIFO
enable
Int
status
Word
length
bit-0
DTR*
receive
data
ready
delta
CTS*
bit-0
bit-8
BIT-0
bit-0
bit-0
© 2002 IMP, Inc.