IDT82V3380A Integrated Device Technology, IDT82V3380A Datasheet - Page 5

• Manufacturer Part Number: IDT82V3380A
• Description: Synchronous Ethernet Idt Wan Plltm Idt82v3380a
• Manufacturer: Integrated Device Technology

Table of Contents
9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 154
PACKAGE DIMENSIONS.................................................................................................................................................... 173
ORDERING INFORMATION................................................................................................................................................ 176
IDT82V3380A
............................................................................................................................................................................................. 177
8.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 152
8.3 HEATSINK EVALUATION .......................................................................................................................................................................... 152
8.4 TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 153
9.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 154
9.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 154
9.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 155
9.4 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 162
9.5 OUTPUT WANDER GENERATION ............................................................................................................................................................ 165
9.6 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 166
9.7 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 167
9.3.1
9.3.2
9.3.3
AMI Input / Output Port ................................................................................................................................................................ 155
9.3.1.1
9.3.1.2
9.3.1.3
CMOS Input / Output Port ............................................................................................................................................................ 157
PECL / LVDS Input / Output Port ................................................................................................................................................ 158
9.3.3.1
9.3.3.2
9.3.3.3
Structure ......................................................................................................................................................................... 155
I/O Level ......................................................................................................................................................................... 155
Over-Voltage Protection ................................................................................................................................................. 157
PECL Input / Output Port ................................................................................................................................................ 158
LVDS Input / Output Port ................................................................................................................................................ 160
Single-Ended Input for Differential Input ........................................................................................................................ 161
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SYNCHRONOUS ETHERNET WAN PLL™
September 30, 2010