IDT82V3380A Integrated Device Technology, IDT82V3380A Datasheet - Page 39

• Manufacturer Part Number: IDT82V3380A
• Description: Synchronous Ethernet Idt Wan Plltm Idt82v3380a
• Manufacturer: Integrated Device Technology

3.12
performance of the device output clocks.
/ T4_APLL_BW[1:0] bits respectively. The lower the bandwidth is, the
better the jitter and wander performance of the T0/T4 APLL output are.
T4 DPLL outputs, as selected by the T0_APLL_PATH[3:0] /
T4_APLL_PATH[3:0] bits respectively.
device output.
Table 24: Related Bit / Register in Chapter 3.12
3.13
altogether.
3.13.1
following technologies:
Functional Description
IDT82V3380A
T0_APLL_PATH[3:0]
T4_APLL_PATH[3:0]
T0_APLL_BW[1:0]
T4_APLL_BW[1:0]
A T0 APLL and a T4 APLL are provided for a better jitter and wander
The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0]
The input of the T0/T4 APLL can be derived from one of the T0 and
Both the APLL and DPLL outputs are provided for selection for the
The device supports 9 output clocks and 2 frame sync output signals
The device provides 9 output clocks.
According to the output port technology, the output ports support the
OUT1 ~ OUT5 and OUT9 output a CMOS signal.
• AMI;
• PECL/LVDS;
• CMOS.
Bit
T0 / T4 APLL
OUTPUT CLOCKS & FRAME SYNC SIGNALS
OUTPUT CLOCKS
T0_DPLL_APLL_PATH_CNFG
T4_DPLL_APLL_PATH_CNFG
T0_T4_APLL_BW_CNFG
Register
Address (Hex)
6A
55
60
39
OUT6_PECL_LVDS bit and the OUT7_PECL_LVDS bit respectively.
derived from the T0/T4 DPLL and T0/T4 APLL outputs, and the corre-
sponding OUTn_PATH_SEL[3:0] bits (1 ≤ n ≤ 7). The derived signal can
be from the T0/T4 DPLL and T0/T4 APLL outputs, as selected by the
corresponding OUTn_PATH_SEL[3:0] bits (1 ≤ n ≤ 7). If the signal is
derived from one of the T0/T4 DPLL outputs, please refer to
the output frequency. If the signal is derived from the T0/T4 APLL output,
please refer to
as selected by the OUT8_PATH_SEL bit. After being divided automati-
cally, the output is of 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz, as
selected by the 400HZ_SEL bit. Its duty cycle is 50:50 or 5:8, as deter-
mined by the AMI_OUT_DUTY bit.
as selected by the OUT9_PATH_SEL bit. After being divided automati-
cally, the output is of 2.048 MHz or 1.544 MHz, as selected by the
IN_SONET_SDH bit.
be affected by the status of the T4 input clock. It is determined by the
OUT8_EN / OUT9_EN and T4_INPUT_FAIL
Refer to
mined by the corresponding OUTn_INV bit (1 ≤ n ≤ 7 or n = 9).
aligned with the T0/T4 selected input clock respectively every 125 µs
period.
OUT6 and OUT7 output a PECL or LVDS signal, as selected by the
OUT8 outputs an AMI signal.
The outputs on OUT1 ~ OUT7 are variable, depending on the signals
The output on OUT8 is derived from T0 or T4 DPLL 77.76 MHz path,
The output on OUT9 is derived from T0 or T4 DPLL 16E1/16T1 path,
The outputs on OUT8 and OUT9 can be enabled or disabled, or may
The outputs on OUT1 to OUT7 and OUT9 can be inverted, as deter-
All the output clocks derived from T0/T4 selected input clock are
Table
29.
Table 26~Table 28
SYNCHRONOUS ETHERNET WAN PLL™
for the output frequency.
1
/ T4_INPUT_FAIL
September 30, 2010
Table 25
2
bits.
for