IDT82V3380A Integrated Device Technology, IDT82V3380A Datasheet - Page 13

• Manufacturer Part Number: IDT82V3380A
• Description: Synchronous Ethernet Idt Wan Plltm Idt82v3380a
• Manufacturer: Integrated Device Technology

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Pin Description
IDT82V3380A
Table 1: Pin Description
SONET/SDH
FF_SRCSW
EX_SYNC1
IN5_POS
IN5_NEG
MS/SL
Name
OSCI
RST
IN1
IN2
IN3
IN4
PIN DESCRIPTION
Pin No.
100
10
18
99
74
45
24
25
46
47
40
41
pull-down
pull-down
pull-down
pull-down
pull-down
pull-up
pull-up
I/O
I
I
I
I
I
I
I
I
I
I
I
PECL/LVDS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
AMI
AMI
Frame Synchronization Input Signal
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the master
clock for the device.
FF_SRCSW: External Fast Selection Enable
During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH)
bit determines whether the External Fast Selection is enabled.
High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is enabled);
Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is disabled).
After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection is
enabled:
High: Pair IN3 / IN5 is selected.
Low: Pair IN4 / IN6 is selected.
After reset, the input on this pin takes no effect if the External Fast selection is disabled.
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit (b0, 13H), controls whether the device is configured
as the Master or as the Slave. Refer to
The signal level on this pin is reflected by the MASTER_SLAVE bit (b1, 09H).
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will still
be held in reset state for 500 ms (typical).
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
IN1: Input Clock 1
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
IN2: Input Clock 2
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
IN3: Input Clock 3
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN4: Input Clock 4
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN5_POS / IN5_NEG: Positive / Negative Input Clock 5
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz or 622.08
MHz clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
Single-ended input for differential input is also supported. Refer to
Input for Differential
Global Control Signal
Input Clock
13
Input.
3
3
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
Chapter 3.14 Master / Slave Configuration
Description
SYNCHRONOUS ETHERNET WAN PLL™
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Chapter 9.3.3.3 Single-Ended
September 30, 2010
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for details.
. The EXT_SW