IDT70V27 Integrated Device Technology, IDT70V27 Datasheet - Page 9

• Manufacturer Part Number: IDT70V27
• Description: 32k X 16 3.3v Dual-port Ram
• Manufacturer: Integrated Device Technology

Waveform of Read Cycles
BUSY
DATA
Timing of Power-Up Power-Down
NOTES:
1. Timing depends on which signal is asserted last: CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first: CE, OE, LB, or UB.
3. t
4. Start of valid data depends on which timing becomes effective last t
5. SEM = V
6. Refer to Chip Enable Truth Table.
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
UB, LB
BUSY has no relation to valid output data.
ADDR
BDD
R/W
OUT
OUT
CE
OE
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
(6)
IH
.
I
I
CE
CC
SB
(6)
t
t
t
t
AA
ACE
AOE
t
LZ
ABE
(4)
(1)
t
(4)
(4)
PU
(4)
(5)
AOE
50%
t
RC
, t
ACE
, t
t
BDD
AA
9
or t
(3,4)
BDD
.
VALID DATA
Commercial and Industrial Temperature Range
t
PD
(4)
50%
3603 drw 06
t
HZ
(2)
t
OH
,
3603 drw 05