IDT70V27 Integrated Device Technology, IDT70V27 Datasheet - Page 11

• Manufacturer Part Number: IDT70V27
• Description: 32k X 16 3.3v Dual-port Ram
• Manufacturer: Integrated Device Technology

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing
NOTES:
1. R/W or CE or UB and LB must be HIGH during all address transitions.
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
9. To access RAM, CE = V
10. Refer to Chip Enable Truth Table.
CE or SEM
CE or SEM
ADDRESS
ADDRESS
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
DATA
UB or LB
UB or LB
2).
on the bus for the required t
specified t
DATA
WR
DATA
is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
R/W
R/W
OUT
OE
IN
IN
WP
(9,10)
(9)
(9)
(9,10)
.
IL
and SEM = V
DW
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
t
AS
EW
t
(6)
AS
or t
(6)
IH
WP
. To access semaphore, CE = V
(4)
) of a LOW CE and a LOW R/W for memory array writing cycle.
t
WZ
(7)
t
t
AW
AW
t
t
WC
WC
t
t
EW
WP
(2)
(2)
IH
and SEM = V
11
t
t
DW
DW
WP
IL
. t
or (t
EW
Commercial and Industrial Temperature Range
WZ
must be met for either condition.
t
+ t
WR
DW
(3)
) to allow the I/O drivers to turn off and data to be placed
t
t
t
DH
DH
WR
t
OW
(3)
t
HZ
(7)
(4)
(1,5,8)
3603 drw 08
3603 drw 07
(1,5)