IDT70V27 Integrated Device Technology, IDT70V27 Datasheet - Page 2

• Manufacturer Part Number: IDT70V27
• Description: 32k X 16 3.3v Dual-port Ram
• Manufacturer: Integrated Device Technology

Description:
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
address, and I/O pins that permit independent, asynchronous access for
Pin Configurations
NOTES:
1. All V
2. All V
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM,
The device provides two independent ports with separate control,
DD
SS
pins must be connected to ground supply.
pins must be connected to power supply.
07/29/04
INDEX
I/O
I/O
I/O
I/O
I/O
I/O
SEM
R/W
CE
CE
A
A
A
A
A
UB
OE
V
LB
A
V
V
NC
NC
NC
10L
11L
12L
13L
14L
15L
14L
13L
12L
11L
10L
DD
SS
SS
9L
0L
1L
L
L
L
L
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(1,2,3)
100-PIN TQFP
TOP VIEW
IDT70V27PF
PN100-1
2
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (
circuitry of each port to enter a very low standby power mode.
these devices typically operate on only 500mW of power. The IDT70V27
is packaged in a 100-pin Thin Quad Flatpack (TQFP) and a 144-pin Fine
Pitch BGA (fp BGA).
(4)
(5)
Fabricated using IDT’s CMOS high-performance technology,
Commercial and Industrial Temperature Range
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CE
3603 drw 02
0
A
A
A
A
A
A
NC
NC
NC
LB
UB
CE
CE
SEM
R/W
OE
I/O
I/O
I/O
I/O
I/O
I/O
and
V
V
V
10R
11R
12R
13R
14R
9R
SS
SS
SS
R
15R
14R
13R
12R
11R
10R
R
0R
1R
R
CE
R
R
1
) permits the on-chip