IDT70V27 Integrated Device Technology, IDT70V27 Datasheet - Page 14

• Manufacturer Part Number: IDT70V27
• Description: 32k X 16 3.3v Dual-port Ram
• Manufacturer: Integrated Device Technology

DATA
Timing Waveform of Write with Port-to-Port Read and BUSY
Timing Waveform Write with BUSY (M/S = V
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. If M/S = V
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. t
DATA
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
ADDR
ADDR
WH
WB
BUSY
R/W
L
OUT "B"
is only for the "Slave" version.
must be met for both BUSY input (SLAVE) and output (MASTER).
= CE
IN "A"
IL
"A"
"A"
"B"
"B"
for the reading port.
R
IL
= V
(SLAVE), then BUSY is an input. Then for this example BUSY "
IL
(refer to Chip Enable Truth Table).
t
APS
(1)
BUSY
R/W
R/W
"B"
"B"
"A"
"B"
, until BUSY
APS
is ignored for M/S = V
"B"
t
goes HIGH.
WB
t
BAA
(3)
MATCH
t
IL
WC
A
"= V
14
(SLAVE).
t
WP
IH
(2)
and BUSY "
t
WP
IL
Commercial and Industrial Temperature Range
B
"= input is shown above.
)
t
MATCH
DW
t
WDD
VALID
t
WH
(1)
3603 drw 12
t
DDD
(3)
(2,5)
t
,
BDA
,
t
DH
(M/S = V
3603 drw 11
t
BDD
VALID
IH
)
(4)