IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 6

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

MBUS[2]
MBUS[3]
MBUS[4]
MBUS[5]
MBUS[6]
MBUS[7]
MBUS[8]
MBUS[9]
MBUS[10]
MBUS[11]
MDATA[0]
MDATA[1]
MDATA[2]
IDT77V011
65
64
63
61
60
59
58
57
56
55
81
82
83
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
I/O
I/O
I/O
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[3]).
Reset
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[4]).
Reset
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[5]).
Reset
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[6]).
Reset
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[7]).
Reset
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[8]).
Reset
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[9]).
Reset
UTOPIA 2 Address bus (LSB+9).
Utility Bus Utility bus PHY chip select (CS[10]).
Reset
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[11]).
Reset
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[12]).
Reset
UTOPIA 2 Management interface data bus [LSB].
Utility Bus Utility Bus address and data bus [LSB].
UTOPIA 2 Management interface data bus [LSB+1].
Utility Bus Utility Bus address and data bus [LSB+1].
UTOPIA 2 Management interface data bus [LSB+2].
Utility Bus Utility Bus address and data bus [LSB+2].
TxSIZE[2] - number of bytes to remove from cell in transmit direction (MSB).
TxLOC - Location of Tx TAG in cell. "0" TAG located at beginning of cell, "1" TAG located at end of cell.
TxHEC - Add HEC placeholder. "0" do not add placeholder, "1" add placeholder.
RxSIZE[0] - Number of bytes to add to cell in the receive direction (LSB).
RxSIZE[1] - Number of bytes to add to cell in the receive direction (LSB + 1).
RxSIZE[2] - Number of bytes to add to cell in the receive direction (MSB).
RxLOC - Location of TAG in cell in the receive direction. RxLOC = "0" TAG located at beginning of cell,
TxLOC = "1" TAG located at end of cell.
RxHEC - Remove HEC from cell. "0" do not remove HEC, "1" remove HEC.
DPI Bus Size. Indicates whether DPI transmit and receive bus is 4-bits or 8-bits wide. "0" 4-bit DPI bus, "1"
8-bit DPI bus.
UTOPIA Bus Size. Indicates whether the UTOPIA transmit and receive data bus is 8-bits or 16-bits wide. "0"
8-bit UTOPIA bus, "1" 16-bit UTOPIA bus.
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March 15, 2001