IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 23

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

5 5 5 5 H H H H F H L
address into the receive subport address field. The 77V011 uses the
subport field in determining how to route the cell. Normal cells have a
PHY subport value from zero to the value stored in Max Subports bits of
the Configuration 2 register. The Max Subport can be any value between
zero and 30, as the UTOPIA 2 specification allows a total of 31 PHY
ports to be connected to a UTOPIA 2 interface.
Stream™ Subport bits of the Subport Configuration 1 register. In order
for In-Stream™ cells to be filtered properly two things must happen.
First, the subport value within the received cell must match the In-
Stream™ Subport, Tx Subport Width, Tx Byte Location, and the Tx Bit
Location register fields. Second, the received cell's header, excluding
the PT, CLP and HEC fields, must match the In-Stream™ Cell Header
register bits [31:4]. This dual check allows the In-Stream™ subport
value to be the same as a valid PHY subport address.
what byte of the header the subport field starts in. Valid values are zero
to three without using a TAG, and zero to seven when using a TAG. The
subport field can start in any byte location of the header. This value is
programmed at reset with TxADDR[2:0] pins. The 77V011 will concate-
nate the receive subport field if any part of the subport field extends into
the payload area of the cell. This is to ensure that the payload will not be
altered.
tion. This value indicates what bit in the byte the subport MSB is located
in. A value of zero means that bit zero of the selected byte is MSB, bit 7
of the next byte is MSB-1, etc.... The subport can start on any bit of a
byte and span multiple bytes.
Mode Select 8006
PIN Controls 801A
IDT77V011
The receive cell routing is done by inserting the originating PHY port
In-Stream™ cells have a subport value that is defined in the In-
The Rx Byte Location bits of the Rx Subport Position register indicate
Bits [5:3] of the Rx Subport Position register contain the Rx Bit Loca-
F H L Y Y Y Y H H H H & H O O
F H L
F H L
& H O O 5 5 5 5 R R R R X W L Q J
& H O O
& H O O
4
3
4
5
6
7
X W L Q J
X W L Q J
X W L Q J
Init from EEPROM 0 - 1
EEPROM Mux
Select
EEPROM Clock
Out
EEPROM Chip
Select
EEPROM Out
EEPROM In
0 - 1
0 - 1
0 - 1
0 - 1
0 - 1
Table 13 Pin Configuration Table
Defined by pin Five byte write from EEPROM to In-Stream™ Cell Header and In-
0
0
0
0
0
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programmed in the Rx Subport Width field bits of the Subport Configura-
tion 2 register. The subport width can be any value between one and
five, with the default value being five.
field, default value is 0x000000. This 24-bit value is used to compare
against the incoming cell headers on the receive UTOPIA 2 interface. A
bit wise AND operation is done between each bit of the incoming cell
header and its corresponding bit of the Rx Out of Range Address Mask
register. The Address Range Error bit of the Status register will be set to
a one if the result of any of these AND operations is a one, indicating an
invalid cell has been received. A Notification cell will be generated if the
Rx Address Error bit of the Notification Mask register is set to a one.
Another Notification cell will be generated 25ms after the error occurred
if the Address Range Error bit has not been cleared. Additional Notifica-
tion cells will be generated on 12ms intervals, thereafter, until the
Address Range Error bit is cleared.
register stores the subport address of the violating Rx Out of Range cell.
The CPU can read this register to determine what PHY port the invalid
cell came from. The Rx Out of Range Subport bits will be overwritten
when a new address range error occurs.
Error bit of the Status register. Writing a one will clear the interrupt and
reset the register bit to a zero.
Receive Cell Routing Register Table.
The number of bits to be used for the receive subport field is
The Rx Out of Range Address Mask registers validate the VPI/VCI
Clearing the interrupt is done by writing a one to the Address Range
Registers associated with the receive cell routing are defined in the
The Rx Out of Range Subport bits of the Rx Out of Range Subport
Stream™ Subport registers at reset. "0" do not write five byte value, "1"
write five byte value to registers.
Indicates if the EEPROM interface will be connected to the internal logic or
the EEPROM registers. "0" connected to internal logic, "1" connected to
EEPROM registers.
EEPROM clock when EEPROM interface is connected to the EEPROM
registers. "0" clock low, "1" clock high.
EEPROM chip select when EEPROM interface is connected to the
EEPROM registers. "0" EEPROM interface is selected, "1" EEPROM inter-
face is not selected.
EEPROM registers.
EEPROM serial input when EEPROM interface is connected to the
EEPROM registers.
EEPROM serial output when EEPROM interface is connected to the
March 15, 2001