IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 15

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

3 3 3 3 U U U U R R R R J U J U J U J U D P P L Q J 3 L Q
5 5 5 5 H H H H J L V W H
MGMT[3:2] and TxADDR[3:0] signals, on the PCB, to select desired
register values. The SYSRST signal must be asserted for at least one
SYSCLK cycle to load the desired values. On the rising edge of
SYSRST the 77V011 will begin loading the register values, which takes
an additional 16 SYSCLK cycles. During this 16 clock cycle period all
outputs will be tri-stated.
3 3 3 3 U U U U R R R R J U J U J U J U D P P L Q J 3 L Q
5 5 5 5 H H H H J L V W H
registers to Read/Write registers. Writing a one to the Override Pin
Configuration bit of the Pin Controls register will change the pin config-
urable registers from Read only to Read/Write. This allows the 77V011
configuration parameters to be changed during normal operation. See
Pin Configuration Table for register description.
5 5 5 5 H H H H V H W 2 S W L R Q V
Reset command (Message Type ID 0x3) will reset the 77V011 and the
PHY devices. The SYSRST pin must be asserted low for a minimum of
MBUS[2:0]
MBUS[3]
MBUS[4]
MBUS[7:5]
MBUS[8]
MBUS[9]
MBUS[10]
MBUS[11]
MGMT[2]
MGMT[3]
TxADDR[2:0]
TxADDR[3]
IDT77V011
Pull-up or pull-down resistors must be connected to MBUS[11:0],
The 77V011 has the option to change the Read only pin configurable
The System Reset (SYSRST) pin or an In-Stream™ cell carrying the
V H W 2 S W L R Q V
V H W 2 S W L R Q V
J L V W H
J L V W H
J L V W H U U U U V V V V D D D D W W W W 5 5 5 5 H V H W
J L V W H
J L V W H
J L V W H U U U U V D I W H U
V H W 2 S W L R Q V
D P P L Q J 3 L Q
D P P L Q J 3 L Q
D P P L Q J 3 L Q & R Q I L J X U D
D P P L Q J 3 L Q
D P P L Q J 3 L Q
D P P L Q J 3 L Q & R Q I L J X U D
V D I W H U
V D I W H U
V D I W H U 5 5 5 5 H V H W
Tx TAG Size
Tx TAG Location
Tx Add HEC
Rx TAG Size
Rx TAG Location
Rx HEC
DPI Size
UTOPIA 2 Size
MMODE
DPI Mode
Subport Byte Location
Init from EEPROM
H V H W
H V H W
H V H W
H V H W
H V H W
H V H W
& R Q I L J X U D
& R Q I L J X U D
& R Q I L J X U D E O H
& R Q I L J X U D
& R Q I L J X U D
& R Q I L J X U D E O H
Transmit and receive subport address location. Indicates what byte of the header the transmit
Number of bytes to remove from the cell. Valid values are from zero to four bytes.
Location of the transmit TAG. "0" transmit TAG located at the beginning of the cell, "1" trans-
mit TAG located at the end of the cell.
Add a HEC placeholder to the cell. "0" do not add HEC placeholder, "1" add HEC placeholder. Tx TAG [3]
Number of bytes to add to the cell. Valid values are from zero to four bytes.
Location of the receive TAG. "0" receive TAG located at the beginning of the cell, "1" receive
TAG located at the end of the cell.
Remove HEC byte from cell. "0" do not remove HEC byte, "1" remove HEC byte.
DPI bus size. "0" 4-bit transmit and receive data bus, "1" 8-bit transmit and receive data bus. Mode Select [0]
UTOPIA 2 bus size. "0" 8-bit transmit and receive data bus, "1" 16-bit transmit and receive
data bus.
Management mode. "0" Utility Bus style, "1" UTOPIA 2 style.
DRxCLK direction. "0" switch mode (output), "1" normal mode (input).
and receive subport addresses are located in. Valid values are zero to three.
Five byte write from EEPROM to In-Stream™ Cell Header and In-Stream™ Subport registers
at reset. "0" do not write five byte value, "1" write five byte value.
E O H
E O H
E O H
E O H
E O H
E O H
Table 5 Reset Configuration Pins
15 of 43
100ns, while the In-Stream™ (internal) reset command will keep the
77V011 in reset for 35 SYSCLK cycles.
deassertion of SYSRST, or the internal reset in the case of a Reset
command. All outputs will be tri-stated starting two SYSCLK cycles after
the assertion of SYSRST or the internal reset, and will stay tri-stated for
24 SYSCLK cycles after the deassertion of SYSRST or internal reset.
The PHYRST pin will then assert low resetting the PHY devices for eight
additional SYSCLK cycles. After the eight clock cycle period PHYRST
pin will deassert high. Eight clock cycles may not be long enough to
properly reset some PHY devices. In this case a pull down resistor
should be connected to the PHYRST pin. This will allow the PHYRST
pin to be asserted as soon as it is tri-stated, which will Lenten the time
that the PHYRST pin is a logical zero.
bit of the Reset register. Writing a one will force the external PHYRST
pin low for 16 SYSCLK cycles. This register bit will return to zero once
the reset command is completed. This method will only reset the PHY
device connected to the PHYRST pin.
% D Q G Z L G W K D Q G & O R F N 6 S H H G V
DPI clocks must run at 40MHz, or greater, to achieve 155.52Mbps data
rate with overhead. The Clock Speed vs. Bandwidth Table lists some of
the possible data rates and the clock frequencies required to achieve
them.
The 77V011 will remain in reset for 16 SYSCLK cycles after the
The PHY can be reset at any time by writing a one to the PHY Reset
The 77V011 can run at a maximum SYSCLK speed of 50MHz. The
Tx TAG [2:0]
Rx TAG [3]
Mode Select [1]
Tx TAG [4]
Rx TAG [2:0]
Rx TAG [4]
Mode Select [2]
Mode Select [3]
Tx Subport Position
[2:0] and Rx Subport
Position [2:0]
Mode Select [4]
March 15, 2001