IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 38

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

, Q W H
, Q W H U U U U Q D O
, Q W H
, Q W H
Device ID
Configuration 1
Configuration 2
Configuration 3
Tx TAG
Rx TAG
IDT77V011
Q D O 5 5 5 5 H H H H J L V W H U
Q D O
Q D O
J L V W H U 0 0 0 0 D S D S D S D S
J L V W H U
J L V W H U
8000
8001
8002
8003
8004
8005
[7:0]
0
1
2
3
[7:4]
[1:0]
[6:2]
7
[7:0]
[2:0]
3
4
[2:0]
3
4
Device Version
Number
Drop Tx Cell
Copy EFCI
Rx Move PT/
CLP
Tx Move PT/CLP 0
Not Used
Stall Tx
Max Subports
Not Used
Stall Tx Cycles
Tx TAG Size
Tx Add HEC
Tx TAG Location Defined by
[7:5]
Rx TAG Size
Rx Remove HEC Defined by
Rx TAG Location Defined by
[7:5]
Table 25 Internal Register Map (Part 1 of 4)
0x0
0x1E
0xFF
0x10
0
0
0
Defined by
pin
Defined by
pin
pin
Not Used
Defined by
pin
pin
pin
Not Used
38 of 43
This is the device version number. 77V011 = 0x10.
"Selects whether or not to drop cell with invalid Subport Address. "0" do not
drop the cell, "1" drop the cell."
"Selects whether or not to OR the EFCI bit of the cell header with the EFCI
bit of the 4-byte TAG area appended to the beginning of the cell, and place
the OR’ed EFCI bit in the cell header. This option is not valid when the TAG
is appended to the end of the cell. "0" do not OR the EFCI bit to the 4-byte
TAG area, "1" OR the EFCI bit to the 4-byte TAG area."
"Selects whether or not to move the PT/CLP fields from the cell header into
the 4-byte TAG area appended to the beginning of the cell. This option is
not valid when the TAG is appended to the end of the cell. "0" do not move
the PT/CLP to the 4-byte TAG area, "1" move the PT/CLP to the 4-byte TAG
area. "
"Selects whether or not to move the PT/CLP fields from the 4-byte TAG
area appended to the beginning of the cell into the cell header. This option
is not valid when the TAG is appended to the end of the cell. "0" do not
move the PT/CLP fields to the cell header, "1" move the PT/CLP fields to
the cell header."
"Selects whether or not to stall the pipeline if the PHY transmit FIFO is full.
"0" drop the cell, "1" stall the pipeline indefinitely, "2" stall the pipeline for
Stall Cycles."
Indicates the maximum subport address value for the PHY(s) connected to
the transmit UTOPIA II interface.
Number of TCLK cycles the interface has to stall the pipeline when the PHY
transmit FIFO is full. This field is valid only if the Stall Pipeline for Stall
Cycles option is selected.
Number of bytes to remove from the ATM cell in the transmit direction. Valid
values are from zero to four.
"Add a HEC placeholder in the transmit direction. "0" do not add a HEC
placeholder, "1" add a HEC placeholder."
"TAG location in transmit direction. "0" transmit TAG is located at the begin-
ning of the cell, "1" transmit TAG is located at the end of the cell."
Number of bytes to add to ATM cell in the receive direction. Valid values are
from zero to four.
"Remove HEC byte from cell. "0" do not remove the HEC byte from the cell,
"1" remove the HEC byte from the cell."
"TAG location in receive direction. "0" receive TAG is located at the begin-
ning of the cell, "1" receive TAG is located at the end of the cell."
March 15, 2001