IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 10

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

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(SYSCLK). The frequency at which each output clock operates is
dependent on the SYSCLK frequency and on the width of the DPI and
UTOPIA 2 interfaces. See Clock Relationship Table for the relationship
between SYSCLK and the output clocks.
SYSCLK. The DRxCLK clock domain within the 77V011 will run at the
same frequency as the DRxCLK pin.
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face, as specified by the UTOPIA Level 2 specification. The interface is
a UTOPIA master and will operate with either an 8-bit or 16-bit Input
Data Bus (RxDATA[15:0]). UTOPIA cell level handshake is used to
receive ATM cells from the PHY device. The other signals associated
with this interface are Receive Start of Cell (RSOC), Receive Enable
(RENB), Receive Cell Available (RCLAV), Receive Clock (RCLK),
Receive Address Bus (RxADDR[4:0]) and Receive LED (RxLED).
ates according to the MPHY Cell-Level Handshake with one RCLAV, as
described in the UTOPIA Level 2 specification.
defined in the Clock Relationship and Frequency Table.
signal asserts high when a cell is transferred over the bus and will stay
high for 2
MBUS[11] signal. Setting MBUS[11] to a zero will select a 8-bit bus,
while setting MBUS[11] to a one will select a 16-bit bus. The value of
MBUS[11], at reset, is stored in the UTOPIA 2 Size bit of the Mode
Select register. See the UTOPIA 2 Receive Register Table for register
description.
fashion. The Max Subports field of the Configuration 2 register deter-
mines the upper boundary of the polled addresses. The default value of
the Max Subports field is 0x1E, which is also the maximum valid PHY
address. The user should not program a value of 0x1F, as this is defined
as a Null PHY port by the UTOPIA 2 specification.
the polling sequence is to output the Null PHY subport address (0x1F)
on one RCLK cycle and then output a valid PHY subport address on the
next RCLK cycle. This sequence is repeated starting at PHY port
address 0x00 and ending at the value specified in Max Subports field.
The 77v011 will wrap back to address 0x00 once it has polled the Max
Subports address. A PHY device is selected when a PHY responds to
its subport address by asserting RCLAV high. RENB will assert on the
same RCLK cycle that RCLAV is asserted, assuming there is no valid
cell transfer in progress. The 77V011 will resume polling starting with the
IDT77V011
All clocks within the 77V011 are derived from the System Clock
When DRxCLK is configured as an input it is totally asynchronous to
The 77V011 offers a fully compliant UTOPIA Level 2 receive inter-
The RxADDR[4:0] bus is fully UTOPIA Level 2 compliant and oper-
RCLK is a continuous clock, whose relationship to SYSCLK is
RxLED indicates if there is activity on the RxDATA[15:0] bus. This
UTOPIA transmit and receive bus size is selected at reset with the
Polling on the UTOPIA 2 receive bus is done in a round robin
When there is no cell transfer in progress, no PHY port is selected,
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RCLK cycles. AT 40MHz this is approximately 0.1seconds.
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next sequential subport address once the cell transfer to a selected
PHY port begins.
the 77V011 will continue to place the responding PHY subport address
on the RxADDR[4:0] bus until the current cell transfer has ended and
the responding PHY is given control of the bus. For example, if PHY
0x03 responds by asserting RCLAV while PHY 0x08 is still transferring a
cell, then the 77V011 will continue to place PHY subport address 0x03
on the RxADDR[4:0] bus. This will continue until PHY 0x08 has finished
its cell transfer and PHY 0x03 is given control of the receive bus. Polling
will then resume with PHY subport address 0x04.
an input to the 77V011 and the frequency of DRxCLK is low enough to
cause the UTOPIA receive bus to interrupt the cell transfer. The inter-
ruption will be indicated by RENB de-asserting high during the cell
transfer. Data transfer will resume, where it left off, when RENB re-
asserts low. In order to resume the current cell transfer the same PHY
subport address is placed on the RxADDR[4:0] bus one RCLK cycle
before RENB is re-asserted low. Each time a cell transfer is interrupted
the polling sequence is interrupted in this manner, which may happen
frequently if DRxCLK is much slower than SYSCLK. For example if PHY
port 0x03 is given control of the bus to transfer a cell. Once PHY port
0x03 takes control of the bus the 77V011 begins its polling sequence
starting with PHY port 0x04. In the middle of the cell transfer data is
halted by RENB de-asserting high, due to the DPI interface. At this time
data transfer is halted while 77V011 is polling PHY port 0x08. After
some period of time the DPI interface starts to transfer the remainder of
the cell. The 77V011 puts the PHY subport address 0x03 on the
RxADDR[4:0] bus and then asserts RENB low on the next RCLK cycle.
Data transfer resumes where it had left off and the 77V011 starts polling
the PHY ports starting at PHY subport address 0x09.
between back to back cells when a TAG is not being used, and a
maximum seven clock cycle delay when a four byte TAG is used. In 16-
bit mode there is a maximum one clock cycle delay between back to
back cells when a TAG is not being used, and a maximum five clock
cycle delay when a four byte TAG is used.
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face, as specified by the UTOPIA Level 2 specification. This is a master
UTOPIA interface that uses UTOPIA cell level handshake to transmit
ATM cells to the PHY device. It will operate with either a 8-bit or 16-bit
Output Data Bus (TxDATA[15:0]). Other signals associated with this
interface are Transmit Start of Cell (TSOC), Transmit Enable (TENB),
Transmit Clock (TCLK), Transmit Cell Available (TCLAV), Transmit
Reference Clock (TxREF), Reference Clock (REFCLK), Transmit Parity
(TxPRTY), Transmit Address Bus (TxADDR[4:0]) and Transmit LED
(TxLED).
Clock Relationship and Frequency Table.
When a PHY port responds with a high RCLAV during a cell transfer
A variance in the polling state machine may occur when DRxCLK is
In 8-bit UTOPIA mode there is a maximum one clock cycle delay
The 77V011 offers a fully compliant UTOPIA Level 2 transmit inter-
TCLK is a continuous clock, whose relationship is defined in the
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March 15, 2001