IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 17

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

0 D Q
0 D Q D D D D J H P H Q W
0 D Q
0 D Q
and write to the PHY registers during normal operation, and to configure
the pin configurable registers during reset.
(BMODE), Management Bus (MBUS[11:0]), Management Data Bus
(MDATA[7:0]), Management 1 (MGMT[1]), Management 2 (MGMT[2]),
Management 3 (MGMT[3]), Management 4 (MGMT[4]), Management 5
(MGMT[5]), PHY Reset (PHYRST) and PHY Interrupt (PHYINT).
the PHY registers. The 77V011 will operate in either a Utility Bus mode
or the Management Mode described in the UTOPIA 2 mode section
A2.4.2 of the UTOPIA Level 2 specification.
registers.
8 W L O L W \ % X V 0 R G H
Read and write commands are sent to the PHY with In-Stream™
programming cells.
used to select a particular PHY device. These are active low signals
used to validate read, write, or addressing operations on the Utility Bus.
(AD[7:0]) used to address, read and write data on the Utility Bus.
validate read, write, or addressing operations on the Utility Bus.
read data from an addressed location on MDATA[7:0].
Mode Select 8006
PHY Reset
IDT77V011
The Management interface is a multi-function interface used to read
During normal operation the Management Interface is used to access
Refer to the Address Map for addressing description of the PHY
The Utility Bus is used to access and configure the PHY registers.
MBUS[11:0] are active low Chip Select Enable (CS[12:1]) signals
MDATA[7:0] is a multiplexed byte wide address and data bus
MGMT[1] is an active low Chip Select Enable (CS[0]) signal used to
MGMT[2] is an active low Read Enable (RD) used as an enable to
Signals associated with the Management Interface are Bus Mode
J H P H Q W , , , , Q W H U
J H P H Q W
J H P H Q W
(O)
(O)
(O)
(O)
8007
(I)
Add/Data[7:0]
SYSCLK
PHYCS
ALE
WR
Q W H U I I I I D F D F D F D F H H H H
Q W H U
Q W H U
t
PALE
3
0
UTOPIA Manage-
ment Mode
PHY Reset
t
ALPW
t
AAL
0 - 1
0 - 1
Figure 13 Utility Bus Write Operation
t
Address
AW
Table 9 Pin Configuration Table
t
ALA
t
PPHY
t
ALW
Defined by pin Selects type of management interface to use. "0" Utility bus style, "1"
0
17 of 43
write data to an addressed location on MDATA[7:0].
the address in the address phase of a Utility Bus read or write
command.
asserted by writing to the PHY Reset bit in the PHY Reset register.
PHY layer and indicates that an interrupt has occurred. The interrupt
must be cleared by the controlling CPU before another interrupt event
can be reported. Registers associated with the management interface
are described in the Management Register Table.
8 W L O L W
8 W L O L W
8 W L O L W
8 W L O L W \ \ \ \ % X V
Once the 77V011 interprets the cell as a read command it will drive
PHYCS, ALE, RD, and AD[7:0]. The PHY samples the address on the
falling edge of ALE. Once PHYCS and RD assert the bus tristates and
switches to an input for the PHY to place data on. The PHY drives the
bus until the rising edge of PHYCS or RD. One Utility Bus read can
include up to 32 bytes of data.
8 W L O L W
8 W L O L W
8 W L O L W
8 W L O L W \ \ \ \ % X V : U L W H 2 S H
Once the 77V011 interprets the cell as a write command it will drive
PHYCS, ALE, WR, and AD[7:0]. The PHY samples the address on the
falling edge of ALE. Once PHYCS and WR assert the 77V011 will write
data to the PHY. One Utility Bus write can include up to 32 bytes of data.
MGMT[5] is an active high Address Latch Enable (ALE) used to latch
PHYRST is an active low PHY reset signal. PHYRST can be
PHYINT is an active low interrupt signal. This signal is driven by the
A Utility bus read is initiated by an In-Stream™ programming cell.
A Utility bus write is initiated by an In-Stream™ programming cell.
MGMT[3] is an active low Write Enable (WR) used as an enable to
UTOPIA 2 management style.
(PHYRST signal will be asserted low for at least 16 SYSCLK cycles).
PHY Reset. "0" do not reset the PHY device, "1" reset the PHY device
t
WRPW
Write Data to PHY
t
DWS
% X V
% X V 5 5 5 5 H D G 2 S H
% X V : U L W H 2 S H
% X V : U L W H 2 S H U U U U D D D D W L W L W L W L R R R R Q Q Q Q
% X V
% X V : U L W H 2 S H
H D G 2 S H
H D G 2 S H
H D G 2 S H U U U U D D D D W L R Q
t
DWH
W L R Q
W L R Q
W L R Q
March 15, 2001
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