IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 20

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

IDT77V011
BMODE
MBUS[11:0]
MDATA[7:0]
MGMT[1]
MGMT[2]
MGMT[3]
MGMT[4]
PHYRST
PHYINT
MGMT[5]
PHYRST
PHYINT
MGMT[1]
MBUS[11:0]
MGMT[2]
MGMT[3]
MGMT[5]
MDATA[7:0]
PHYINT
PHYRST
BMODE
ADDR[11:0]
DATA[7:0]
SEL
RD/DS
WR/RW
RDY/DTACK
PHYRST
PHYINT
CS[0]
CS[12:1]
RD
WR
ALE
ADDR/DATA[7:0]
PHYINT
PHYRST
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Table 10 Multiplexed Management Interface (Part 2 of 2)
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Table 11 Utility Bus Management Interface
Table 12 UTOPIA 2 Management Interface
ALE
PHYRST
PHYINT
20 of 43
Bus Mode. "0" selects Motorola management mode interface, "1" selects Intel
management mode interface.
Address bus used to select a register in a particular PHY device.
Byte wide bidirectional data bus.
Select. Active low signal used to validate ADDR[11:0] for a read or write opera-
tion.
Read or Data Strobe. If BMODE = "0" then read data from the PHY layer, or
strobe write data to the PHY layer. If BMODE ="1" then read data from the
addressed location onto the DATA[7:0] bus.
Write or Read/Write. If BMDOE ="0" then access is a read if high and a write if
low. If BMODE ="1" then write data from DATA[7:0] to the addressed location.
Ready or Data Acknowledge. Tri-stateable signal used to acknowledge the end
of a transfer over DATA[7:0] bus.
PHY Reset. Active low PHY layer reset.
PHY Interrupt. PHY layer interrupt, with open-drain active low output.
Chip Select[0]. Active low PHY chip select.
Chip Select[12:1]. Active low PHY chip select for 12 additional PHYs con-
nected to this device.
Read Enable. Active low read enable.
Write Enable. Active low write enable.
Address Latch Enable. Active high address latch enable.
Address/Data bus. Bidirectional address and data bus.
PHY Interrupt. Active low PHY interrupt.
PHY Reset. Active low PHY layer reset.
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PHYRST
PHYINT
March 15, 2001