ST72F264G ST Microelectronics, ST72F264G Datasheet - Page 74

• Manufacturer Part Number: ST72F264G
• Description: (ST72F260G - ST72F264G) 8-BIT MCU
• Manufacturer: ST Microelectronics

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DataSheet
ST72260G, ST72262G, ST72264G
11.4 SERIAL PERIPHERAL INTERFACE (SPI)
11.4.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
11.4.2 Main Features
Figure 47. Serial Peripheral Interface Block Diagram
74/171
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
MOSI
MISO
CPU
SCK
4
SS
U
/2 max. slave mode frequency
.com
SOD
bit
SPIDR
8-Bit Shift Register
Read Buffer
SERIAL CLOCK
CPU
GENERATOR
CONTROL
MASTER
/4 max.)
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Data/Address Bus
Read
Write
11.4.3 General Description
Figure 47
(SPI) block diagram. There are 3 registers:
The SPI is connected to external devices through
3 pins:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
– SS: Slave select:
put by SPI slaves
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master
7
SPIE
SPIF WCOL
7
SPE
shows the serial peripheral interface
SPR2
CONTROL
OVR
STATE
SPI
Interrupt
request
MODF
MSTR
CPOL
0
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CPHA
SOD
Device
SS
SPICR
SPICSR
SSM
SPR1
.
0
1
SPR0
SSI
0
0
4U
4U.com
4U
.com
.com
.com