ST72F264G ST Microelectronics, ST72F264G Datasheet - Page 30

• Manufacturer Part Number: ST72F264G
• Description: (ST72F260G - ST72F264G) 8-BIT MCU
• Manufacturer: ST Microelectronics

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ST72260G, ST72262G, ST72264G
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit the HALT modes (see column “Exit from
HALT” in “Interrupt Mapping” table). When several
pending interrupts are present while exiting HALT
mode, the first one serviced can only be an inter-
rupt with exit from HALT mode capability and it is
selected through the same decision process
shown in
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 19. Concurrent Interrupt Management
Figure 20. Nested Interrupt Management
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Figure
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MAIN
MAIN
RIM
RIM
18.
IT2
IT2
IT1
IT1
IT4
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TLI
TLI
IT1
IT4
IT0
IT0
7.4 CONCURRENT & NESTED MANAGEMENT
The following
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0. The software priority is giv-
en for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: TLI (Top Level Interrupt) is not available in
this product.
IT3
IT3
IT1
20. The interrupt hardware priority is given
IT4
IT2
Figure 19
10
10
SOFTWARE
PRIORITY
LEVEL
SOFTWARE
PRIORITY
LEVEL
MAIN
MAIN
and
3
3
3
3
3
3
3/0
3
3
2
1
3
3
3/0
Figure 20
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I1
I1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 0
0 1
1 1
1 1
show two
I0
I0
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