ST72F264G ST Microelectronics, ST72F264G Datasheet - Page 23

• Manufacturer Part Number: ST72F264G
• Description: (ST72F260G - ST72F264G) 8-BIT MCU
• Manufacturer: ST Microelectronics

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DataSheet
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
level specified for the selected f
A proper reset signal for a slow rising V
can generally be provided by an external RC net-
work connected to the RESET pin.
Figure 13. RESET Sequences
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
4
V
V
U
IT+(LVD)
IT-(LVD)
.com
RUN
V
DD
ACTIVE PHASE
DD
RESET
LVD
is over the minimum
OSC
frequency.
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DD
RUN
t
h(RSTL)in
supply
WATCHDOG UNDERFLOW
ACTIVE
PHASE
EXTERNAL
RESET
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
The device RESET pin acts as an output that is
pulled low when V
V
The LVD filters spikes on V
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
DD
Power-On RESET
Voltage Drop RESET
<V
IT-
INTERNAL RESET (4096 T
VECTOR FETCH
(falling edge) as shown in
ST72260G, ST72262G, ST72264G
RUN
ACTIVE
PHASE
WATCHDOG
RESET
t
w(RSTL)out
w(RSTL)out
DD
<V
DD
CPU
IT+
RUN
.
)
larger than t
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(rising edge) or
Figure
Figure
g(VDD)
13.
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