ST72F264G ST Microelectronics, ST72F264G Datasheet - Page 70

• Manufacturer Part Number: ST72F264G
• Description: (ST72F260G - ST72F264G) 8-BIT MCU
• Manufacturer: ST Microelectronics

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DataSheet
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read Only (except bit 2 R/W)
Reset Value: xxxx x0xx (xxh)
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
70/171
ICF1
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
7
4
U
OCF1
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TOF
ICF2 OCF2 TIMD
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0
0
0
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
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