DT28F016SV-080 Intel Corporation, DT28F016SV-080 Datasheet - Page 8

• Manufacturer Part Number: DT28F016SV-080
• Description: 16-MBIT (1 MBIT x 16/ 2 MBIT x 8) FlashFile MEMORY
• Manufacturer: Intel Corporation

28F016SV FlashFile™ MEMORY
Each block can be written and erased a minimum
of 100,000 cycles. Systems can achieve one
million Block Erase Cycles by providing wear-
leveling algorithms and graceful block retirement.
These techniques have already been employed in
many flash file systems and hard disk drive
designs.
The 28F016SV incorporates two Page Buffers of
256 bytes (128 words) each to allow page data
programs. This feature can improve a system
program performance by up to 4.8 times over
previous flash memory devices, which have no
Page Buffers.
All operations are started by a sequence of
Program commands to the device. Three Status
Registers (described in detail later in this
datasheet) and a RY/BY# output pin provide
information on the progress of the requested
operation.
While the 28F008SA requires an operation to
complete before the next operation can be
requested, the 28F016SV allows queuing of the
next operation while the memory executes the
current
overhead when writing several bytes in a row to
the array or erasing several blocks at the same
time. The 28F016SV can also perform program
operations
performing erase of another block.
The 28F016SV provides selectable block locking
to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S
or
associated nonvolatile lock-bit which determines
the lock status of the block. In addition, the
28F016SV has a master Write Protect pin (WP#)
which prevents any modifications to memory
blocks whose lock-bits are set.
The 28F016SV contains three types of Status
Registers to accomplish various functions:
8
A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory Status Register. The CSR, when used
alone, provides a straightforward upgrade
capability to the 28F016SV from a 28F008SA-
based design.
A Global Status Register (GSR) which informs
the system of command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
Application
operation.
to one block
Code.
This
Each
eliminates
of
block
memory
has
system
while
an
The GSR and BSR memory maps for byte-wide
and word-wide modes are shown in Figures 5
and 6.
The 28F016SV incorporates an open drain
RY/BY# output pin. This feature allows the user to
OR-tie many RY/BY# pins together in a multiple
memory configuration such as a Resident Flash
Array.
Other configurations of the RY/BY# pin are
enabled via special CUI commands and are
described in detail in the 16-Mbit Flash Product
Family User’s Manual.
The
Information
additional
previously did not offer. This command uploads
the Device Revision Number, Device Proliferation
Code and Device Configuration Code to the page
buffer. The Device Proliferation Code for the
28F016SV is 01H, and the Device Configuration
Code identifies the current RY/BY# configuration.
Section 4.4 documents the exact page buffer
address locations for all uploaded information. A
subsequent Page Buffer Swap and Page Buffer
Read command sequence is necessary to read
the correct device information.
The 28F016SV also incorporates a dual chip-
enable function with two input pins, CE
CE
functionality as the regular chip-enable pin, CE#,
on the 28F008SA. For minimum chip designs,
CE
use CE
uses the logical combination of these two signals
to enable or disable the entire chip. Both CE
CE
either one becomes inactive, the chip will be
disabled. This feature, along with the open drain
RY/BY# pin, allows the system designer to reduce
the number of control pins used in a large array of
16-Mbit devices.
The
read/programs to the 28F016SV. BYTE# at logic
low selects 8-bit mode with address A
between the low byte and high byte. On the other
hand, BYTE# at logic high enables 16-bit
operation with address A
32 Block Status Registers (BSRs) which
provide block-specific status information such
as the block lock-bit status.
1
1
1
#. These pins have exactly the same
# may be tied to ground and system logic may
# must be active low to enable the device. If
BYTE#
28F016SV’s
0
# as the chip enable input. The 28F016SV
information
command
pin
allows
enhanced
1
that
provides
becoming the lowest
either
the
Upload
E
x8
access
0
28F016SA
selecting
or
0
Device
0
# and
# and
x16
to