DT28F016SV-080 Intel Corporation, DT28F016SV-080 Datasheet - Page 20

• Manufacturer Part Number: DT28F016SV-080
• Description: 16-MBIT (1 MBIT x 16/ 2 MBIT x 8) FlashFile MEMORY
• Manufacturer: Intel Corporation

28F016SV FlashFile™ MEMORY
NOTES:
1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register memory maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
3. A
4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size, and to avoid writing the
5. In x16 mode, only the lower byte DQ
6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure RY/BY# output to one of three pulse-modes or enable and disable the RY/BY# function.
9. Program address, PA, is the Destination address in the flash array which must match the Source address in the Page
10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.
11. After writing the Upload Device Information command and the Confirm command, the following information is output at
12. To ensure that the 28F016SV’s power consumption during sleep mode reaches the deep power-down current level, the
13. The upper byte of the data bus (DQ
20
actual lock-bit status.
A
Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.
Buffer. Refer to the 16-Mbit Flash Product Family User’s Manual .
Page Buffer addresses specified below:
A page buffer swap followed by a page buffer read sequence is necessary to access this information. The contents of all
other Page Buffer locations, after the Upload Device Information command is written, are reserved for future implementation
by Intel Corporation. See Section 4.8 for a description of the Device Configuration Code. This code also corresponds to
data written to the 28F016SV after writing the RY/BY# Reconfiguration command.
system also needs to de-select the chip by taking either or both CE
0
0
is automatically complemented to load second byte of data. BYTE# must be at V
value determines which WD/BC is supplied first: A
Address
06H, 07H (Byte Mode)
03H (Word Mode)
1EH (Byte Mode)
0FH (DQ
1FH (Byte Mode)
0FH (DQ
0–7
8–15
)(Word Mode)
)(Word Mode)
8–15
0–7
) during command writes is a “Don’t Care” in x16 operation of the device.
is used for WCL and WCH. The upper byte DQ
0
= 0 looks at the WDL/BCL, A
Information
Device Revision Number
Device Revision Number
Device Configuration Code
Device Configuration Code
Device Proliferation Code (01H)
Device Proliferation Code (01H)
0
# or CE
1
# high.
IL
0
.
= 1 looks at the WDH/BCH.
8–15
is a don’t care.
E