DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 93

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

9
9.1 JTAG Description
The DS3105 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public
instructions included are HIGHZ, CLAMP, and IDCODE.
the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary
Scan Architecture:
The TAP has the necessary interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS. Details on these pins
can be found in Table 6-5. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.1-
1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 9-1. JTAG Block Diagram
9.2 JTAG TAP Controller State Machine Description
This section discusses the operation of the TAP controller state machine. The TAP controller is a finite state
machine that responds to the logic level at JTMS on the rising edge of JTCLK. Each of the states denoted in
9-2
Test-Logic-Reset. Upon device power-up, the TAP controller starts in the Test-Logic-Reset state. The instruction
register contains the IDCODE instruction. All system logic on the device operates normally.
Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction register and
all test registers remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the
controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the Select-
IR-SCAN state.
Capture-DR. Data can be parallel-loaded into the test register selected by the current instruction. If the instruction
does not call for a parallel load or the selected test register does not allow parallel loads, the register remains at its
current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or to the Exit1-
DR state if JTMS is high.
are described in the following paragraphs.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
JTAG TEST ACCESS PORT AND BOUNDARY SCAN
10k
JTDI
Test Access Port (TAP)
TAP Controller
Instruction Register
10k
JTMS
IDENTIFICATION
TEST ACCESS PORT
INSTRUCTION
BOUNDARY
REGISTER
REGISTER
REGISTER
REGISTER
CONTROLLER
BYPASS
DEVICE
SCAN
JTCLK
Preliminary. Subject to Change Without Notice.
10k
JTRST
SELECT
TRI-STATE
Bypass Register
Boundary Scan Register
Device Identification Register
93 of 110
Figure 9-1
JTDO
shows a block diagram. The DS3105 contains
DS3105
Figure