DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 77

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bit 7: MFSYNC Enable (MFSEN). This configuration bit enables the 2 kHz output on the MFSYNC pin. See
section 7.8.2.5.
Bit 6: FSYNC Enable (FSEN). This configuration bit enables the 8 kHz output on the FSYNC pin. See section
7.8.2.5.
Register Name:
Register Description:
Register Address:
Name
Default
Bits 3 to 0: T4 APLL Frequency (T4FREQ[3:0]). When T0CR1:T4APT0=0, this field configures the T4 APLL DFS
frequency. The T4 APLL DFS frequency affects the frequency of the T4 APLL which in turn affects the available
output frequencies on the output clock pins (see the registers). See section 7.8.2. The default value of this field is
controlled by the O6F[2:0] and O3F[2:0] pins as described in
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0 = Disabled, driven low
1 = Enabled, output is 2 kHz
0 = Disabled, driven low
1 = Enabled, output is 8 kHz
T4FREQ[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1100 - 1111
MFSEN
Bit 7
Bit 7
1
--
0
T4 APLL DFS Frequency
APLL output disabled
77.76 MHz
24.576 MHz (12 x E1)
32.768 MHz (16 x E1)
37.056 MHz (24 x DS1)
24.704 MHz (16 x DS1)
68.736 MHz (2 x E3)
44.736 MHz (DS3)
25.248 MHz (4 x 6312 kHz)
62.500 MHz (GbE ÷ 16)
30.720 MHz (3 x 10.24)
40.000 MHz (4 x 10 MHz)
26.000 MHz (2 x 13 MHz)
{unused values}
Bit 6
--
0
FSEN
Bit 6
1
OCR4
Output Configuration Register 4
63h
T4CR1
the T4 DPLL Configuration Register 1
64h
Preliminary. Subject to Change Without Notice.
Bit 5
Bit 5
--
0
0
0
77 of 110
Bit 4
Bit 4
--
0
0
0
T4 APLL Frequency (4 x T4 APLL DFS)
Disabled, output is low
311.04 MHz (4 x 77.76 MHz)
98.304 MHz (48 x E1)
131.072 MHz (64 x E1)
148.224 MHz (96 x DS1)
98.816 MHz (64 x DS1)
274.944 MHz (8 x E3)
178.944 MHz (4 x DS3)
100.992 MHz (16 x 6312 kHz)
250.000 MHz (GbE ÷ 4)
122.880 MHz (12 x 10.24)
160.000 MHz (16 x 10 MHz)
104.000 MHz (8 x 13 MHz)
{unused values}
Table
7-16.
Bit 3
Bit 3
0
0
Bit 2
Bit 2
0
0
T4FREQ[3:0]
see below
Bit 1
Bit 1
0
0
Bit 0
Bit 0
DS3105
0
0