DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 49

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bit 7: Phase Alarm (PALARM). This real-time status bit indicates the state of the T0 DPLL phase lock detector.
See section 7.7.6. (NOTE: This is not the same as T0STATE=Locked.)
Bit 6: Disable 180 (D180). When locking to a new reference, the T0 DPLL first tries nearest-edge locking (±180°)
for the first two seconds. If unsuccessful it then tries full phase/frequency locking (±360°). Disabling the nearest-
edge locking can reduce lock time by up to two seconds but may cause an unnecessary phase shift (up to 360°)
when the new reference is close in frequency/phase to the old reference. See section 7.7.5.
Bit 4: Resync Analog Dividers (RA). When this bit is set the analog output dividers are always synchronized to
ensure that low-frequency outputs are in sync with the higher-frequency clock from the DPLL.
Bit 3: Leave set to zero (test control).
Bit 2: 8kHz Edge Polarity (8KPOL). Specifies the input clock edge to lock to on the selected reference when it is
configured for LOCK8K mode. See section 7.4.2.
Bit 1: Leave set to zero (test control).
Bit 0: Leave set to zero (test control).
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0 = T0 DPLL phase-lock parameters are met (FLEN, CLEN, NALOL, FLLOL)
1 = T0 DPLL loss of phase lock
0 = normal operation: try nearest-edge locking then phase/frequency locking
1 = phase/frequency locking only
0 = synchronized for the first two seconds after power-up
1 = always synchronized
0 = Falling edge
1 = Rising edge
PALARM
Bit 7
0
D180
Bit 6
0
TEST1
Test Register 1 (Not Normally Used)
03h
Preliminary. Subject to Change Without Notice.
Bit 5
—
0
49 of 110
Bit 4
RA
1
Bit 3
0
0
8KPOL
Bit 2
1
Bit 1
0
0
Bit 0
DS3105
0
0