DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 89

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bits 7 to 6: Phase Lock Timeout Multiplier (PHLKTOM[1:0]). This field is an unsigned integer that specifies the
resolution of the phase lock timeout field PHLKTO[5:0].
Bits 5 to 0: Phase Lock Timeout (PHLKTO[5:0]). This field is an unsigned integer that, together with the
PHLKTOM[1:0] field, specifies the length of time that the T0 DPLL attempts to lock to an input clock before
declaring a phase lock alarm (by setting the corresponding LOCK bit in the
seconds is PHLKTO[5:0] * 2^(PHLKTOM[1:0]+1). The state machine remains in the Pre-locked, Pre-locked 2 or
Phase-lost modes for the specified time before declaring a phase alarm on the selected input. See section 7.7.1.
Register Name:
Register Description:
Register Address:
Name
Default
Bit 6 to 4: SYNC12 Source (SYNCSRC). This field determines whether the SYNC1 and SYNC2 pins are
associated with the selected input clock or forced to be associated with a specific input clock. See section 7.9.7.
Bit 3: 8 kHz Invert (8KINV). When this bit is set to 1 the 8 kHz signal on clock output FSYNC is inverted. See
section 7.8.2.5.
Bit 2: 8 kHz Pulse (8KPUL). When this bit is set to 1, the 8 kHz signal on clock output FSYNC is pulsed rather
than 50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of FSYNC is equal to
the clock period of OC3. See section 7.8.2.5.
Bit 1: 2 kHz Invert (2KINV). When this bit is set to 1 the 2 kHz signal on clock output MFSYNC is inverted. See
section 7.8.2.5.
Bit 0: 2 kHz Pulse (2KPUL). When this bit is set to 1, the 2 kHz signal on clock output MFSYNC is pulsed rather
than 50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of MFSYNC is equal to
the clock period of OC3. See section 7.8.2.5.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
00 = 2 seconds
01 = 4 seconds
10 = 8 seconds
11 = 16 seconds
0XX = SYNC1 pins associated with T0 DPLL selected reference IC3 or IC5, SYNC2 pin associated with T0
1X0 = SYNC1 pin associated with IC3, SYNC2 pin associated with IC4
1X1 = SYNC1 pin associated with IC5, SYNC2 pin associated with IC6
0 = FSYNC not inverted
1 = FSYNC inverted
0 = FSYNC not pulsed; 50% duty cycle
1 = FSYNC pulsed, with pulse width equal to OC3 period
0 = MFSYNC not inverted
1 = MFSYNC inverted
0 = MFSYNC not pulsed; 50% duty cycle
1 = MFSYNC pulsed, with pulse width equal to OC3 period
Bit 7
DPLL selected reference IC4 or IC6
Bit 7
--
0
PHLKTOM[1:0]
0
Bit 6
Bit 6
0
0
PHLKTO
Phase Lock Timeout Register
79h
FSCR1
Frame Sync Configuration Register 1
7Ah
SYNCSRC[2:0]
Preliminary. Subject to Change Without Notice.
Bit 5
Bit 5
0
1
89 of 110
Bit 4
Bit 4
1
0
8KINV
Bit 3
Bit 3
0
0
PHLKTO[5:0]
ISR
8KPUL
Bit 2
Bit 2
0
0
registers). The timeout period in
2KINV
Bit 1
Bit 1
1
0
2KPUL
Bit 0
Bit 0
DS3105
0
0