DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 59

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

DIVN=1 and LOCK8K=1: (Alternate direct-lock frequency decode)
Register Name:
Register Description:
Register Address:
Name
Default
Bits 5 to 2: Input Clock Valid Control (IC6 to IC3). These control bits can be used to force input clocks to be
considered invalid. If a clock is invalidated by one of these control bits it will not appear in the priority table in the
PTAB1 and PTAB2 registers, even if the clock is otherwise valid. These bits are useful when system software
needs to force clocks to be invalid in response to OAM commands. Note that setting a VALCR bit low has no effect
on the corresponding bit in the
Register Name:
Register Description:
Register Address:
Name
Default
Bit 0: Input Clock Valid Control (IC9). This bit has the same behavior as the bits in
clock.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0000 = 10 MHz (internally divided down to 5 MHz)
0001 = 25 MHz (internally divided down to 5 MHz)
0010 = 62.5 MHz (internally down to 31.25 MHz)
0011 = 125 MHz (internally down to 31.25 MHz)
0100 = 156.25 MHz (differential inputs only. internally divided down to 31.25 MHz)
0101 to 1111 = undefined
FREQ[3:0] Default Values:
ICR3 – ICR4:
ICR5 – ICR9:
0 = Force invalid
1 = Don’t force invalid; determine validity normally
Bit 7
Bit 7
--
1
--
0
Bit 6
Bit 6
--
--
0
0
VALSR
0000b
0011b
VALCR1
Input Clock Valid Control Register 1
30h
VALCR2
Input Clock Valid Control Register 2
31h
Preliminary. Subject to Change Without Notice.
registers. See sections 7.6.2.
Bit 5
Bit 5
IC6
--
1
0
59 of 110
Bit 4
Bit 4
IC5
--
1
0
Bit 3
Bit 3
IC4
--
1
0
Bit 2
Bit 2
IC3
--
1
0
VALCR1
Bit 1
Bit 1
--
--
0
0
but for the IC9 input
Bit 0
Bit 0
DS3105
IC9
--
0
1