PM5364 pmc-sierra, PM5364 Datasheet - Page 84

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

10.2.3
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
When control bytes are present in the data stream, the pointer interpreter is bypassed, and the J1
position and pointer adjustments are determined from these control bytes. This mode can only
be used when the data was Serial TelecomBus (STCB) encoded at the High-order Path
Termination (HPT) level. If the data was scrambled, or was STCB encoded at the Multiplex
Section Termination (MST) level, then the high-order path control bytes are not present.
In Raw mode, the incoming data is treated as a continuous bit sequence. Data is received in
8-bit or 10-bit words. The pointer interpreter is bypassed, and all received data is included in the
PRBS monitoring. The supported data rates (8-bit/10-bit) are 622/777.6 Mbit/s and 2488 Mbit/s
(8-bit).
The incoming PRBS data is tested against the X
optionally inverted before being checked.
The PRBS monitoring process consists of first synchronizing the monitor with the incoming
PRBS data, then generating subsequent expected PRBS words and comparing them with the
incoming PRBS words. If the expected and received words are not equal, then an error has been
detected in that word. This does not count bit errors since multiple bit errors in a word will be
considered as a single word error. Four consecutive word errors will force the monitor out of
synchronization.
Synchronization begins by loading the monitor with consecutive bits from the incoming PRBS
pattern. This requires three words (23 of 24 bits, or 23 of 30 bits). If the following four expected
PRBS words generated by the monitor match the incoming words, then the monitor is
considered synchronized. If a mismatch occurs, then the monitor remains unsynchronized, and
continues to attempt to synchronize by repeating this process with the next words in the data
stream.
The PIPM will not synchronize to the input PRBS data if the data is a sequence of all 0 bits (or
all 1 bits with inverted PRBS).
DMUX_FIFO Block
The DMUX_FIFO block is required to separate an STS-48 equivalent flow into four STS-12
equivalent flows as shown in Figure 14. It is used in the STS-48 slice only. The STS-12 slices of
Figure 13 (three working and three protect) select the output of the associated working or
protect DMUX_FIFO for further processing by blocks downstream of the CML slice when
configured in STS-48 mode. The DMUX_FIFO decouples phase, jitter, and wander between the
77 MHz core clock and the 311 MHz recovered clock from the SERDES block.
The DEMUX_FIFO performs a simple byte de-interleave as shown in Figure 16(a). The OC-12
to OC-48 mode of the ingress STSI blocks reorders the byte de-interleaved streams to generate
SDH compatible STS-12 streams as shown in Figure 16(b).
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
23
+ X
18
+ 1 polynomial. The PRBS data is
Released
84