PM5364 pmc-sierra, PM5364 Datasheet - Page 46

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
9
Pin Description
Table 2 Pin Description
Pin Name
REFCLK
RSTB
CSB
RDB
WRB
Control, Clocking and Microprocessor Bus Interfaces (47 pins)
Type
Input
Input
Input
Input
Input
Pin No.
T33
AP30
AP7
AL7
AP6
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Function
Reference Clock. The Reference Clock, REFCLK,
is an externally generated 77.76 MHz +/-20ppm
clock with a nominal 50% duty cycle.
REFCLK must be frequency locked to the analog
differential reference clock chip inputs
LREFCLK_P/N and SREFCLK_P/N.
REFCLK pin is implemented with programmable
drive I/O. It is controlled by VDDOPROG_E.
Reset Enable Bar. The active low reset signal,
RSTB, provides an asynchronous TUPP 2488
reset. RSTB is a Schmitt triggered input with an
internal pull-up resistor of 30 to 50 kOhms. It is
recommended to use an external pull-up resistor of
4.7 kOhms The device must be reset after power
up.
Chip Select Bar. The active low chip select signal,
CSB, controls microprocessor access to registers
in the TUPP 2488 device. CSB is set low during
TUPP 2488 Microprocessor Interface Port register
accesses. CSB is set high to disable
microprocessor accesses.
If CSB is not required (i.e. register accesses
controlled using RDB and WRB signals only), CSB
should be connected to an inverted version of the
RSTB input.
Read Enable Bar. The active low read enable bar
signal, RDB, controls microprocessor read
accesses to registers in the TUPP 2488 device.
RDB is set low and CSB is also set low during
TUPP 2488 Microprocessor Interface Port register
read accesses. The TUPP 2488 drives the D[15:0]
bus with the contents of the addressed register
while RDB and CSB are low.
Write Enable Bar. The active low write enable bar
signal, WRB, controls microprocessor write
accesses to registers in the TUPP 2488 device.
WRB is set low and CSB is also set low during
TUPP 2488 Microprocessor Interface Port register
write accesses. The contents of D[15:0] are
clocked into the addressed register on the rising
edge of WRB while CSB is low.
Released
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