PM5364 pmc-sierra, PM5364 Datasheet - Page 224

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

13.11.4
13.11.5
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Figure 58 Output Waveform using Pre-emphasis
This increased amplitude of bits following transitions helps to counteract frequency dependent
attenuation incurred with transmission over PCB traces and cables. The high speed RASIO
CML transmitter provides programmable ratios of VswHigh to VswLow to provide optimal
performance over a wide range of trace lengths.
For guidance on the usage of pre-emphasis, refer to Application Note PMC-2021098.
Receive equalization boosts the high frequency content of received signals, counteracting some
of the high frequency attenuation incurred with transmission over PCB traces and cables. The
RASIO CML receiver provides 3 levels for equalization – no equalization, low equalization,
and high equalization level.
High Equalization (RECEIVE_EQ_MODE = 10b) is the default for most applications.
However, some system designs may see improved performance with a different Receive
Equalization configuration. For guidance on the optimization of receive equalization, refer to
Application Note PMC-2021098.
The LVPECL LREFCLK and SREFCLK inputs require AC coupling capacitors between the
inputs and the clock source as shown in Figure 59. The LVPECL REFCLK inputs are internally
biased and have internal termination resistors therefore no external biasing or terminating
resistors for the receiver are required. Resistors are still required to bias the outputs of the
LVPECL clock source (Note: Rt value is dependent on the LVPECL driver).
Receive Equalization
LVPECL REFCLK Inputs
TXOP
TXON
Transition
1
First bit after
Transition
VswHigh
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
0
No Transition
VswLow
0
Released
224