PM5364 pmc-sierra, PM5364 Datasheet - Page 252

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

14.4
14.5
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Receive Serial Buses
Figure 68 shows the relative timing of the receive serial TelecomBus links. Links carry
SONET/SDH frame octets that are encoded in 8B/10B characters. Frame boundaries,
justification events and alarm conditions are encoded in special control characters. The
upstream devices sourcing the links share a common clock and have a common transport frame
alignment that is synchronized by the Receive Serial Interface Frame Pulse signal (J0FP).
RJ0FP in the case of the Line side of TUPP 2488 bus is IJ0. In the case of the System Egress,
RJ0FP is SYSTEM_EGRESS_REF_DLY after EJ0. Due to phase noise of clock multiplication
circuits and backplane routing discrepancies, the links will not phase aligned to each other
(within a tolerance level of 16+8=24 byte times) but are frequency locked. The delay from
RJ0FP being sampled high to the first and last J0 character is shown in Figure 68. In this
example, the first J0 is delivered by one of the four protection links
(RNPROT[4:1]/RPPROT[4:1]). The delay to the last J0 represents the time when the all the
links have delivered their J0 character. In the example below, one of the auxiliary links is shown
to be the slowest (RNWRK[4:1]/RPWRK[4:1]). The minimum value for the internal
programmable delay is the delay to the last J0 character plus 15. The maximum value is the
delay to the first J0 character plus 31. Consequently, the external system must ensure that the
relative delays between all the receive RASIO™ CML links be less than 16 bytes. The relative
phases of the links in Figure 68 are shown for illustrative purposes only.
Figure 68 Receive Serial TelecomBus Link Timing
RASIO™ CML Functional Timing
Every one of the 77.76 MByte/s STS12 transmit channels received carries a byte-stream. These
are named “Parallel Data[7:0]” in Figure 69 and Figure 70and are synchronous to REFCLK.
After CML Subsystem processing eight serial bit-streams are transmitted to the differential
RASIO™ CML pads on the line side, or sixteen serial bit-streams are transmitted to the
differential RASIO™ CML pads on the System side.
RNPROT[Y]/
RPPROT[Y]
RNWRK[X]/
RPWRK[X]
REFCLK
RJ0FP
...
...
Delay to First J0
Delay to Last J0
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
S4,3 / A2
S4,3 / A2
S1,1 / J0
S1,1 / J0
S2,1 / Z0
S2,1 / Z0
Released
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