MT92220BG Zarlink Semiconductor, MT92220BG Datasheet - Page 44

• Manufacturer Part Number: MT92220BG
• Description: Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608
• Manufacturer: Zarlink Semiconductor

44
5.2
The following section summarizes the typical propagation of voice data throughout the MT92220 in the transmit
direction, from the H.110 bus to the packet link.
Data from a TSST is read off the H.110 bus and is associated with either an xxPCM buffer or an HDLC stream by
the TX channel association memory. This memory can associate up to 1023 TSSTs with up to 1023 xxPCM buffers
or 512 HDLC streams. The byte is then treated by the corresponding entry in the TX control memory. In xxPCM,
this structure contains the base address and size of the circular buffer to which the TSST is associated. In HDLC,
this structure also contains the base address and size of the circular buffer, as well as all the internal context used
to perform HDLC de-framing. The byte is then written into its circular buffer.
RX TDM process: Reads bytes from circular buffers and places
RX TDM process: Reads bytes from circular buffers and places
them onto the H.110 bus, inserts idle code in HDLC if no data is
them onto the H.110 bus, inserts idle code in HDLC if no data is
present, pads for underruns/data loss in xxPCM.
present, pads for underruns/data loss in xxPCM.
Tone Copying Process: Copies bytes from each of the 96 tone or
Tone Copying Process: Copies bytes from each of the 96 tone or
silence buffers contained in external RAM to internal memories so
silence buffers contained in external RAM to internal memories so
they can easily be accesses by the RX TDM process.
they can easily be accesses by the RX TDM process.
TX Data Flow
Zarlink Semiconductor Inc.
Figure 19 - Rx Flow 4
TDM Byte (To H.110)
TDM Byte (To H.110)
SSRAM Tone Pair)
SSRAM Tone Pair)
Control Memory
Control Memory
Padding Type
Padding Type
(1 Entry per
(1 Entry per
TONEMEM0
TONEMEM0
Association Memory
Association Memory
(1 entry per TSST)
(1 entry per TSST)
Stream Structure
Stream Structure
Buffer Structure
Buffer Structure
(1 per Stream)
(1 per Stream)
RX Channel
RX Channel
(1 per Bearer)
(1 per Bearer)
RX xxPCM
RX xxPCM
RXTDM0
RXTDM0
RX HDLC
RX HDLC
RXTDM1
RXTDM1
RXTDM1
RXTDM1
Memory (global)
Memory (global)
Buffers (global,
Buffers (global,
Tone Buffer &
Tone Buffer &
Padding Octet
Padding Octet
SSRAM Tone
SSRAM Tone
32 Pairs)
32 Pairs)
Tone Copying
Tone Copying
Process
Process
RX TDM
RX TDM
Process
Process
SDRAM Silence
SDRAM Silence
Buffer Memory
Buffer Memory
SDRAM Silence
SDRAM Silence
Buffers (global,
Buffers (global,
32 of them)
32 of them)
(global)
(global)
Low Latency
Low Latency
Loopback
Loopback
Memory
Memory
(global)
(global)