MT92220BG Zarlink Semiconductor, MT92220BG Datasheet - Page 143

• Manufacturer Part Number: MT92220BG
• Description: Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608
• Manufacturer: Zarlink Semiconductor

Data Sheet
In AAL2, the HDLC Address LUT Structure contains a pointer to a TX Connection Structure as well as the CPS
Timer indicating how much time should pass before an incomplete AAL2 cell is transmitted with this packet. It also
contains the FL (FLush Pending Packet) bit that indicates this packet should always be at the head of an AAL2 cell
(i.e. any pending data should be sent out in another cell).
The format of the AAL2 HDLC Address LUT Structure is the following:
TX Connection
Structure Base for
Address
CPS Timer
FL
N
Field
+(N-2)*4+0
+(N-2)*4+2
+(N-1)*4+0
+(N-1)*4+2
Base address of the TX Connection Structure that will be used to send HDLC packets
with the address shown. When this field is 0000h, the address is deemed invalid and the
packet is discarded.
CPS Timer applied to this packet when it is waiting for cell completion to be transmitted.
Units are in frames.
Flush Pending Packet. When ‘1’, pending packets will be sent in a zero padded cell
before this packet is sent. When ‘0’, normal TX CPS processing will be done to try to
maximize bandwidth utilization.
Number of HDLC addresses supported as defined by Add Range in the HDLC Stream to
HDLC Address LUT Structure.
+0
+2
+4
+6
b15
b14
Figure 79 - HDLC Address LUT (AAL2)
Table 60 - Fields and Description
TX Connection Structure Base [20:5] for Address = N-2
b13
TX Connection Structure Base [20:5] for Address = N-1
TX Connection Structure Base [20:5] for Address = 0
TX Connection Structure Base [20:5] for Address = 1
b12
Zarlink Semiconductor Inc.
b11
CPS Timer [11:0]
CPS Timer [11:0]
CPS Timer [11:0]
CPS Timer [11:0]
b10
b9
b8
Description
b7
b6
b5
b4
b3
b2
b1
1
1
1
1
b0
FL
FL
FL
FL
MT92220
143