MT92220BG Zarlink Semiconductor, MT92220BG Datasheet - Page 30

• Manufacturer Part Number: MT92220BG
• Description: Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608
• Manufacturer: Zarlink Semiconductor

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destination. Both IP packets and AAL2 mini-packets go through this memory. The AAL2 mini-packets are
assembled into cells on the other side of the memory. Packets from the packet assembly module can be routed to
any one of the TX link buffers or to the packet identifier for internal loopback functionality.
Packets going to the disassembly module use a similar scheme: a 2K-byte memory is used for the packets and a
128-byte memory for the handles. In this case, the AAL2 cells are broken down into mini-packets before going to
the memory.
Near the TX link layer interface, the network module uses 512-byte buffers to transfer packets between the SDRAM
and the link layer interfaces. There are 4 buffers used for this purpose: 1 destined to TX link A, 1 to TX link B, 1 from
RX link A and 1 from RX link B. These buffers can be smaller because the system operates flawlessly even if the
entire packet is not contained in the buffer at any one time.
Cells contained in external memory are stored in the SSRAM and free cells are allocated as the various modules
within the chip request them. The cells are also managed in a linked list, in the same way as the packet are.
However, since each cell is individual (i.e. not part of a packet comprised of many blocks) they are only linked when
they are free: when a cell is allocated and contains valid data, its link is not used. Whenever cells are allocated, the
pointer to the cell is added to a cell queue, which contains all cells going to a given destination. The following
figures indicate the format of raw cells in queues, depending on whether the cell is allocated or free:
Multicast Sum
AAL2/AAL5 VC
Number
PN
+1C
+2C
+3C
+10
+14
+18
+20
+24
+28
+30
+34
+38
+C
+0
+4
+8
b31
Field
b30
Multicast Sum
b29
b28
b27
Used in TX. When Cell is queued in multiple TX queues this is decremented each
time the cell is sent and the TX queue that decrements it to 0 frees the cell memory.
In AAL5, this points to a Packet Reassembly structure. In AAL2, this points to an RX
AAL2 VC structure.
FIFO, where cells originated. “00” = RX port A, “01” = RX port B; “10” = TX AAL2;
“11” = TX CPU.
b26
Port Number. Used in RX. Source port of this cell. Used to indicate, in the RX AAL0
b25
b24
b23
b22
Figure 9 - Raw Cell Format (used cell)
Table 9 - Fields and Description
b21
b20
Zarlink Semiconductor Inc.
b19
b18
Cell Header[31:0]
b17
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
PN
b16
b15
Description
b14
b13
b12
b11
AAL2 / AAL5 VC Number [15:0]
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0